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Øyvind Kolås
firmware
Commits
d4ee9f57
Commit
d4ee9f57
authored
Jan 24, 2020
by
schneider
Browse files
feat(max32666): Plug in latest SDK libraries (0.2.1-11)
parent
659362dd
Changes
54
Expand all
Hide whitespace changes
Inline
Side-by-side
epicardium/modules/hardware.c
View file @
d4ee9f57
...
...
@@ -88,7 +88,6 @@ int hardware_early_init(void)
MXC_RTC
,
SQUARE_WAVE_ENABLED
,
F_32KHZ
,
NOISE_IMMUNE_MODE
,
NULL
)
==
E_BUSY
)
;
...
...
lib/card10/card10.c
View file @
d4ee9f57
...
...
@@ -64,7 +64,6 @@ void card10_init(void)
MXC_RTC
,
SQUARE_WAVE_ENABLED
,
F_32KHZ
,
NOISE_IMMUNE_MODE
,
NULL
)
==
E_BUSY
)
;
...
...
lib/sdk/Libraries/Boards/EvKit_V1/Source/board.c
View file @
d4ee9f57
...
...
@@ -140,6 +140,12 @@ int Console_Shutdown(void)
return
E_NO_ERROR
;
}
/******************************************************************************/
int
Console_PrepForSleep
(
void
)
{
return
UART_PrepForSleep
(
ConsoleUart
);
}
/******************************************************************************/
void
NMI_Handler
(
void
)
{
...
...
lib/sdk/Libraries/Boards/EvKit_V1/examples.txt
View file @
d4ee9f57
...
...
@@ -4,7 +4,10 @@ BLE_beacon
BLE_datc
BLE_dats
BLE_fit
BLE_fit_ds
BLE_hci_uart
BLE_scanner
Bootloader
CRC
DES
DMA
...
...
@@ -21,6 +24,7 @@ LP
MAA
OWM
Pulse_Train
RPU
RTC
SDHC_FAT
SDHC_Raw
...
...
@@ -28,6 +32,7 @@ Semaphore
SPI
SPIXF
SPIXR
SPI_DMA
TMR
TRNG
UART
...
...
@@ -35,4 +40,5 @@ USB_CDCACM
USB_CompositeDevice
USB_HIDKeyboard
USB_MassStorage
USB_MassStorage_SDHC
Watchdog
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h
View file @
d4ee9f57
...
...
@@ -262,12 +262,12 @@ typedef struct {
#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS))
/**< CFG_REQSEL Mask */
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL)
/**< CFG_REQSEL_MEMTOMEM Value */
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_MEMTOMEM Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL)
/**< CFG_REQSEL_SPI0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL)
/**< CFG_REQSEL_SPI1RX Value */
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x1UL)
/**< CFG_REQSEL_SPI1RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x
3
UL)
/**< CFG_REQSEL_SPI2RX Value */
#define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x
2
UL)
/**< CFG_REQSEL_SPI2RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI2RX (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI2RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI3RX ((uint32_t)0x3UL)
/**< CFG_REQSEL_SPI3RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI3RX (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI3RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL)
/**< CFG_REQSEL_UART0RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_UART0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL)
/**< CFG_REQSEL_UART1RX Value */
...
...
@@ -280,8 +280,8 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_ADC (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_ADC Setting */
#define MXC_V_DMA_CFG_REQSEL_UART2RX ((uint32_t)0xEUL)
/**< CFG_REQSEL_UART2RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART2RX (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_UART2RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI
3
RX ((uint32_t)0xFUL)
/**< CFG_REQSEL_SPI
3
RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI
3
RX (MXC_V_DMA_CFG_REQSEL_SPI
3
RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI
3
RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI
0
RX ((uint32_t)0xFUL)
/**< CFG_REQSEL_SPI
0
RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI
0
RX (MXC_V_DMA_CFG_REQSEL_SPI
0
RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI
0
RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX ((uint32_t)0x10UL)
/**< CFG_REQSEL_SPI_MSS0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI_MSS0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_USBRXEP1 ((uint32_t)0x11UL)
/**< CFG_REQSEL_USBRXEP1 Value */
...
...
@@ -306,12 +306,12 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_USBRXEP10 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_USBRXEP10 Setting */
#define MXC_V_DMA_CFG_REQSEL_USBRXEP11 ((uint32_t)0x1BUL)
/**< CFG_REQSEL_USBRXEP11 Value */
#define MXC_S_DMA_CFG_REQSEL_USBRXEP11 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_USBRXEP11 Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL)
/**< CFG_REQSEL_SPI0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL)
/**< CFG_REQSEL_SPI1TX Value */
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x21UL)
/**< CFG_REQSEL_SPI1TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x2
3
UL)
/**< CFG_REQSEL_SPI2TX Value */
#define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x2
2
UL)
/**< CFG_REQSEL_SPI2TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI2TX (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI2TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI3TX ((uint32_t)0x23UL)
/**< CFG_REQSEL_SPI3TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI3TX (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI3TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL)
/**< CFG_REQSEL_UART0TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_UART0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL)
/**< CFG_REQSEL_UART1TX Value */
...
...
@@ -322,8 +322,8 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_I2C1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART2TX ((uint32_t)0x2EUL)
/**< CFG_REQSEL_UART2TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART2TX (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_UART2TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI
3
TX ((uint32_t)0x2FUL)
/**< CFG_REQSEL_SPI
3
TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI
3
TX (MXC_V_DMA_CFG_REQSEL_SPI
3
TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI
3
TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI
0
TX ((uint32_t)0x2FUL)
/**< CFG_REQSEL_SPI
0
TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI
0
TX (MXC_V_DMA_CFG_REQSEL_SPI
0
TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI
0
TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX ((uint32_t)0x30UL)
/**< CFG_REQSEL_SPI_MSS0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX << MXC_F_DMA_CFG_REQSEL_POS)
/**< CFG_REQSEL_SPI_MSS0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_USBTXEP1 ((uint32_t)0x31UL)
/**< CFG_REQSEL_USBTXEP1 Value */
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h
View file @
d4ee9f57
...
...
@@ -87,9 +87,6 @@ extern "C" {
*/
typedef
struct
{
__IO
uint32_t
reg0
;
/**< <tt>\b 0x00:</tt> FCR REG0 Register */
__IO
uint32_t
reg1
;
/**< <tt>\b 0x04:</tt> FCR REG1 Register */
__IO
uint32_t
reg2
;
/**< <tt>\b 0x08:</tt> FCR REG2 Register */
__IO
uint32_t
reg3
;
/**< <tt>\b 0x0C:</tt> FCR REG3 Register */
}
mxc_fcr_regs_t
;
/* Register offsets for module FCR */
...
...
@@ -100,9 +97,6 @@ typedef struct {
* @{
*/
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL)
/**< Offset from FCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_FCR_REG1 ((uint32_t)0x00000004UL)
/**< Offset from FCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_FCR_REG2 ((uint32_t)0x00000008UL)
/**< Offset from FCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_FCR_REG3 ((uint32_t)0x0000000CUL)
/**< Offset from FCR Base Address: <tt> 0x000C</tt> */
/**@} end of group fcr_registers */
/**
...
...
@@ -128,60 +122,6 @@ typedef struct {
/**@} end of group FCR_REG0_Register */
/**
* @ingroup fcr_registers
* @defgroup FCR_REG1 FCR_REG1
* @brief Register 1.
* @{
*/
#define MXC_F_FCR_REG1_ACEN_POS 0
/**< REG1_ACEN Position */
#define MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS))
/**< REG1_ACEN Mask */
#define MXC_F_FCR_REG1_ACRUN_POS 1
/**< REG1_ACRUN Position */
#define MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS))
/**< REG1_ACRUN Mask */
#define MXC_F_FCR_REG1_LDTRM_POS 2
/**< REG1_LDTRM Position */
#define MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS))
/**< REG1_LDTRM Mask */
#define MXC_F_FCR_REG1_GAININV_POS 3
/**< REG1_GAININV Position */
#define MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS))
/**< REG1_GAININV Mask */
#define MXC_F_FCR_REG1_ATOMIC_POS 4
/**< REG1_ATOMIC Position */
#define MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS))
/**< REG1_ATOMIC Mask */
#define MXC_F_FCR_REG1_MU_POS 8
/**< REG1_MU Position */
#define MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS))
/**< REG1_MU Mask */
/**@} end of group FCR_REG1_Register */
/**
* @ingroup fcr_registers
* @defgroup FCR_REG2 FCR_REG2
* @brief Register 2.
* @{
*/
#define MXC_F_FCR_REG2_INITTRM_POS 0
/**< REG2_INITTRM Position */
#define MXC_F_FCR_REG2_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_INITTRM_POS))
/**< REG2_INITTRM Mask */
#define MXC_F_FCR_REG2_MINTRM_POS 10
/**< REG2_MINTRM Position */
#define MXC_F_FCR_REG2_MINTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_MINTRM_POS))
/**< REG2_MINTRM Mask */
#define MXC_F_FCR_REG2_MAXTRM_POS 20
/**< REG2_MAXTRM Position */
#define MXC_F_FCR_REG2_MAXTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_MAXTRM_POS))
/**< REG2_MAXTRM Mask */
/**@} end of group FCR_REG2_Register */
/**
* @ingroup fcr_registers
* @defgroup FCR_REG3 FCR_REG3
* @brief Register 3.
* @{
*/
#define MXC_F_FCR_REG3_DONECNT_POS 0
/**< REG3_DONECNT Position */
#define MXC_F_FCR_REG3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_REG3_DONECNT_POS))
/**< REG3_DONECNT Mask */
/**@} end of group FCR_REG3_Register */
#ifdef __cplusplus
}
#endif
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h
View file @
d4ee9f57
...
...
@@ -91,7 +91,8 @@ typedef struct {
__IO
uint32_t
cn
;
/**< <tt>\b 0x08:</tt> FLC CN Register */
__R
uint32_t
rsv_0xc_0x23
[
6
];
__IO
uint32_t
intr
;
/**< <tt>\b 0x024:</tt> FLC INTR Register */
__R
uint32_t
rsv_0x28_0x2f
[
2
];
__I
uint32_t
ecc_data
;
/**< <tt>\b 0x28:</tt> FLC ECC_DATA Register */
__R
uint32_t
rsv_0x2c
;
__IO
uint32_t
data
[
4
];
/**< <tt>\b 0x30:</tt> FLC DATA Register */
__O
uint32_t
acntl
;
/**< <tt>\b 0x40:</tt> FLC ACNTL Register */
}
mxc_flc_regs_t
;
...
...
@@ -107,6 +108,7 @@ typedef struct {
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL)
/**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CN ((uint32_t)0x00000008UL)
/**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL)
/**< Offset from FLC Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_ECC_DATA ((uint32_t)0x00000028UL)
/**< Offset from FLC Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL)
/**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL)
/**< Offset from FLC Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_registers */
...
...
@@ -167,9 +169,6 @@ typedef struct {
#define MXC_F_FLC_CN_LVE_POS 25
/**< CN_LVE Position */
#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS))
/**< CN_LVE Mask */
#define MXC_F_FLC_CN_BRST_POS 27
/**< CN_BRST Position */
#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS))
/**< CN_BRST Mask */
#define MXC_F_FLC_CN_UNLOCK_POS 28
/**< CN_UNLOCK Position */
#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS))
/**< CN_UNLOCK Mask */
#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL)
/**< CN_UNLOCK_UNLOCKED Value */
...
...
@@ -199,6 +198,20 @@ typedef struct {
/**@} end of group FLC_INTR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_ECC_DATA FLC_ECC_DATA
* @brief Flash Controller ECC Data Register.
* @{
*/
#define MXC_F_FLC_ECC_DATA_ECC_EVEN_POS 0
/**< ECC_DATA_ECC_EVEN Position */
#define MXC_F_FLC_ECC_DATA_ECC_EVEN ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_EVEN_POS))
/**< ECC_DATA_ECC_EVEN Mask */
#define MXC_F_FLC_ECC_DATA_ECC_ODD_POS 16
/**< ECC_DATA_ECC_ODD Position */
#define MXC_F_FLC_ECC_DATA_ECC_ODD ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_ODD_POS))
/**< ECC_DATA_ECC_ODD Mask */
/**@} end of group FLC_ECC_DATA_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_DATA FLC_DATA
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h
View file @
d4ee9f57
This diff is collapsed.
Click to expand it.
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h
View file @
d4ee9f57
...
...
@@ -98,7 +98,7 @@ typedef struct {
__I
uint32_t
in
;
/**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO
uint32_t
int_mod
;
/**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
__IO
uint32_t
int_pol
;
/**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
__
R
uint32_t
rsv_0x30
;
__
IO
uint32_t
in_en
;
/**< <tt>\b 0x30:</tt> GPIO IN_EN Register */
__IO
uint32_t
int_en
;
/**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO
uint32_t
int_en_set
;
/**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO
uint32_t
int_en_clr
;
/**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
...
...
@@ -147,6 +147,7 @@ typedef struct {
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL)
/**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL)
/**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL)
/**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL)
/**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL)
/**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL)
/**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL)
/**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
...
...
@@ -347,6 +348,21 @@ typedef struct {
/**@} end of group GPIO_INT_POL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN_EN GPIO_IN_EN
* @brief GPIO Port Input Enable.
* @{
*/
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0
/**< IN_EN_GPIO_IN_EN Position */
#define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS))
/**< IN_EN_GPIO_IN_EN Mask */
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL)
/**< IN_EN_GPIO_IN_EN_DIS Value */
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)
/**< IN_EN_GPIO_IN_EN_DIS Setting */
#define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL)
/**< IN_EN_GPIO_IN_EN_EN Value */
#define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)
/**< IN_EN_GPIO_IN_EN_EN Setting */
/**@} end of group GPIO_IN_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN GPIO_INT_EN
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h
View file @
d4ee9f57
...
...
@@ -107,6 +107,18 @@ typedef struct {
#define MXC_R_HTMR_CTRL ((uint32_t)0x00000010UL)
/**< Offset from HTMR Base Address: <tt> 0x0010</tt> */
/**@} end of group htmr_registers */
/**
* @ingroup htmr_registers
* @defgroup HTMR_SEC HTMR_SEC
* @brief HTimer Long-Interval Counter. This register contains the 32 most significant
* bits of the counter.
* @{
*/
#define MXC_F_HTMR_SEC_RTS_POS 0
/**< SEC_RTS Position */
#define MXC_F_HTMR_SEC_RTS ((uint32_t)(0x7FFFFFFFUL << MXC_F_HTMR_SEC_RTS_POS))
/**< SEC_RTS Mask */
/**@} end of group HTMR_SEC_Register */
/**
* @ingroup htmr_registers
* @defgroup HTMR_SSEC HTMR_SSEC
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h
View file @
d4ee9f57
...
...
@@ -210,39 +210,6 @@ typedef struct {
#define MXC_F_I2C_STATUS_CLK_MODE_POS 5
/**< STATUS_CLK_MODE Position */
#define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS))
/**< STATUS_CLK_MODE Mask */
#define MXC_F_I2C_STATUS_STATUS_POS 8
/**< STATUS_STATUS Position */
#define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS))
/**< STATUS_STATUS Mask */
#define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL)
/**< STATUS_STATUS_IDLE Value */
#define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_IDLE Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL)
/**< STATUS_STATUS_MTX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_MTX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL)
/**< STATUS_STATUS_MRX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_MRX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL)
/**< STATUS_STATUS_MTX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_MTX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL)
/**< STATUS_STATUS_MRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_MRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL)
/**< STATUS_STATUS_SRX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_SRX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL)
/**< STATUS_STATUS_STX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_STX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL)
/**< STATUS_STATUS_SRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_SRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL)
/**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL)
/**< STATUS_STATUS_TX Value */
#define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_TX Setting */
#define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL)
/**< STATUS_STATUS_RX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_RX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL)
/**< STATUS_STATUS_RX Value */
#define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_RX Setting */
#define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL)
/**< STATUS_STATUS_TX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_TX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL)
/**< STATUS_STATUS_NACK Value */
#define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_NACK Setting */
#define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL)
/**< STATUS_STATUS_BY_ST Value */
#define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS)
/**< STATUS_STATUS_BY_ST Setting */
/**@} end of group I2C_STATUS_Register */
/**
...
...
@@ -299,6 +266,12 @@ typedef struct {
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15
/**< INT_FL0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS))
/**< INT_FL0_TX_LOCK_OUT Mask */
#define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22
/**< INT_FL0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS))
/**< INT_FL0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23
/**< INT_FL0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS))
/**< INT_FL0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INT_FL0_Register */
/**
...
...
@@ -355,6 +328,12 @@ typedef struct {
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15
/**< INT_EN0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS))
/**< INT_EN0_TX_LOCK_OUT Mask */
#define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22
/**< INT_EN0_RD_ADDR_MATCH Position */
#define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS))
/**< INT_EN0_RD_ADDR_MATCH Mask */
#define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23
/**< INT_EN0_WR_ADDR_MATCH Position */
#define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS))
/**< INT_EN0_WR_ADDR_MATCH Mask */
/**@} end of group I2C_INT_EN0_Register */
/**
...
...
@@ -369,6 +348,9 @@ typedef struct {
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1
/**< INT_FL1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS))
/**< INT_FL1_TX_UNDERFLOW Mask */
#define MXC_F_I2C_INT_FL1_START_POS 2
/**< INT_FL1_START Position */
#define MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS))
/**< INT_FL1_START Mask */
/**@} end of group I2C_INT_FL1_Register */
/**
...
...
@@ -383,6 +365,9 @@ typedef struct {
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1
/**< INT_EN1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS))
/**< INT_EN1_TX_UNDERFLOW Mask */
#define MXC_F_I2C_INT_EN1_START_POS 2
/**< INT_EN1_START Position */
#define MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS))
/**< INT_EN1_START Mask */
/**@} end of group I2C_INT_EN1_Register */
/**
...
...
@@ -442,6 +427,18 @@ typedef struct {
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1
/**< TX_CTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS))
/**< TX_CTRL0_TX_READY_MODE Mask */
#define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2
/**< TX_CTRL0_TX_AMGC_AFD Position */
#define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS))
/**< TX_CTRL0_TX_AMGC_AFD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3
/**< TX_CTRL0_TX_AMW_AFD Position */
#define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS))
/**< TX_CTRL0_TX_AMW_AFD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4
/**< TX_CTRL0_TX_AMR_AFD Position */
#define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS))
/**< TX_CTRL0_TX_AMR_AFD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5
/**< TX_CTRL0_TX_NACK_AFD Position */
#define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS))
/**< TX_CTRL0_TX_NACK_AFD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7
/**< TX_CTRL0_TX_FLUSH Position */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS))
/**< TX_CTRL0_TX_FLUSH Mask */
...
...
@@ -574,12 +571,6 @@ typedef struct {
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0
/**< SLAVE_ADDR_SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS))
/**< SLAVE_ADDR_SLAVE_ADDR Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10
/**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS))
/**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11
/**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS))
/**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15
/**< SLAVE_ADDR_EX_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS))
/**< SLAVE_ADDR_EX_ADDR Mask */
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h
View file @
d4ee9f57
...
...
@@ -172,7 +172,7 @@ typedef enum {
ECC_IRQn
,
/* 0x62 0x0188 98: Error Correction */
DVS_IRQn
,
/* 0x63 0x018C 99: DVS Controller */
SIMO_IRQn
,
/* 0x64 0x0190 100: SIMO Controller */
RPU
_IRQn
,
/* 0x65 0x0194 101:
RPU
*/
SCA
_IRQn
,
/* 0x65 0x0194 101:
SCA
*/
AUDIO_IRQn
,
/* 0x66 0x0198 102: Audio subsystem */
FLC1_IRQn
,
/* 0x67 0x019C 103: Flash Control 1 */
UART3_IRQn
,
/* 0x68 0x01A0 104: UART 3 */
...
...
@@ -513,13 +513,13 @@ typedef enum {
(p) == MXC_ICC1 ? 1 : -1)
/******************************************************************************/
/* Instruction Cache XIP */
#define MXC_BASE_
ICX
((uint32_t)0x4002F000UL)
#define MXC_
ICX
((mxc_icc_regs_t*)MXC_BASE_
ICX
)
#define MXC_BASE_
SFCC
((uint32_t)0x4002F000UL)
#define MXC_
SFCC
((mxc_icc_regs_t*)MXC_BASE_
SFCC
)
/******************************************************************************/
/* Data Cache */
#define MXC_BASE_
EM
CC ((uint32_t)0x40033000UL)
#define MXC_
EM
CC ((mxc_
em
cc_regs_t*)MXC_BASE_
EM
CC)
#define MXC_BASE_
SR
CC ((uint32_t)0x40033000UL)
#define MXC_
SR
CC ((mxc_
sr
cc_regs_t*)MXC_BASE_
SR
CC)
/******************************************************************************/
/* ADC */
...
...
@@ -810,7 +810,7 @@ typedef enum {
/******************************************************************************/
/* RPU */
#define MXC_BASE_RPU ((uint32_t)0x40002
3
00UL)
#define MXC_BASE_RPU ((uint32_t)0x40002
0
00UL)
#define MXC_RPU ((mxc_rpu_regs_t*)MXC_BASE_RPU)
#define MXC_RPU_NUM_BUS_MASTERS 9
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd
View file @
d4ee9f57
This diff is collapsed.
Click to expand it.
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h
View file @
d4ee9f57
...
...
@@ -87,7 +87,7 @@ extern "C" {
*/
typedef
struct
{
__IO
uint32_t
eccen
;
/**< <tt>\b 0x00:</tt> MCR ECCEN Register */
__
IO
uint32_t
hirc96m
;
/**< <tt>\b 0x04:</tt> MCR HIRC96M Register */
__
R
uint32_t
rsv_0x4
;
__IO
uint32_t
outen
;
/**< <tt>\b 0x08:</tt> MCR OUTEN Register */
__IO
uint32_t
aincomp
;
/**< <tt>\b 0x0C:</tt> MCR AINCOMP Register */
__IO
uint32_t
ctrl
;
/**< <tt>\b 0x10:</tt> MCR CTRL Register */
...
...
@@ -101,7 +101,6 @@ typedef struct {
* @{
*/
#define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL)
/**< Offset from MCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_MCR_HIRC96M ((uint32_t)0x00000004UL)
/**< Offset from MCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL)
/**< Offset from MCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL)
/**< Offset from MCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL)
/**< Offset from MCR Base Address: <tt> 0x0010</tt> */
...
...
@@ -148,17 +147,6 @@ typedef struct {
/**@} end of group MCR_ECCEN_Register */
/**
* @ingroup mcr_registers
* @defgroup MCR_HIRC96M MCR_HIRC96M
* @brief 96MHz Oscillator Trim Register
* @{
*/
#define MXC_F_MCR_HIRC96M_HIRC96MTR_POS 0
/**< HIRC96M_HIRC96MTR Position */
#define MXC_F_MCR_HIRC96M_HIRC96MTR ((uint32_t)(0xFFUL << MXC_F_MCR_HIRC96M_HIRC96MTR_POS))
/**< HIRC96M_HIRC96MTR Mask */
/**@} end of group MCR_HIRC96M_Register */
/**
* @ingroup mcr_registers
* @defgroup MCR_OUTEN MCR_OUTEN
...
...
@@ -223,8 +211,8 @@ typedef struct {
#define MXC_F_MCR_CTRL_P1M_POS 9
/**< CTRL_P1M Position */
#define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS))
/**< CTRL_P1M Mask */
#define MXC_F_MCR_CTRL_
VDDIOH
_SEL_POS
10
/**< CTRL_
VDDIOH
_SEL Position */
#define MXC_F_MCR_CTRL_
VDDIOH_SEL
((uint32_t)(0x1UL << MXC_F_MCR_CTRL_
VDDIOH
_SEL_POS))
/**< CTRL_
VDDIOH
_SEL Mask */
#define MXC_F_MCR_CTRL_
RSTN_VOLTAGE
_SEL_POS 10
/**< CTRL_
RSTN_VOLTAGE
_SEL Position */
#define MXC_F_MCR_CTRL_
RSTN_VOLTAGE_SEL
((uint32_t)(0x1UL << MXC_F_MCR_CTRL_
RSTN_VOLTAGE
_SEL_POS))
/**< CTRL_
RSTN_VOLTAGE
_SEL Mask */
/**@} end of group MCR_CTRL_Register */
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h
View file @
d4ee9f57
...
...
@@ -170,6 +170,9 @@ typedef struct {
#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3
/**< CTRL_STAT_OW_INPUT Position */
#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS))
/**< CTRL_STAT_OW_INPUT Mask */
#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4
/**< CTRL_STAT_OD_SPEC_MODE Position */
#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS))
/**< CTRL_STAT_OD_SPEC_MODE Mask */
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7
/**< CTRL_STAT_PRESENCE_DETECT Position */
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS))
/**< CTRL_STAT_PRESENCE_DETECT Mask */
...
...
lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h
View file @
d4ee9f57
...
...
@@ -91,20 +91,14 @@ typedef struct {
__IO
uint32_t
lpwken0
;
/**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */
__IO
uint32_t
lpwkst1
;
/**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */
__IO
uint32_t
lpwken1
;
/**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */
__IO
uint32_t
lpwkst2
;
/**< <tt>\b 0x14:</tt> PWRSEQ LPWKST2 Register */
__IO
uint32_t
lpwken2
;
/**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */
__IO
uint32_t
lpwkst3
;
/**< <tt>\b 0x1C:</tt> PWRSEQ LPWKST3 Register */
__IO
uint32_t
lpwken3
;
/**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */
__R
uint32_t
rsv_0x24_0x2f
[
3
];
__R
uint32_t
rsv_0x14_0x2f
[
7
];
__IO
uint32_t
lppwst
;
/**< <tt>\b 0x30:</tt> PWRSEQ LPPWST Register */
__IO
uint32_t
lppwen
;
/**< <tt>\b 0x34:</tt> PWRSEQ LPPWEN Register */
__R
uint32_t
rsv_0x38_0x3f
[
2
];
__IO
uint32_t
lpmemsd
;
/**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
__IO
uint32_t
lpvddpd
;
/**< <tt>\b 0x44:</tt> PWRSEQ LPVDDPD Register */
__IO
uint32_t
gp0
;
/**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */
__IO
uint32_t
gp1
;
/**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */
__IO
uint32_t
lpmcstat
;
/**< <tt>\b 0x50:</tt> PWRSEQ LPMCSTAT Register */
__IO
uint32_t
lpmcreq
;
/**< <tt>\b 0x54:</tt> PWRSEQ LPMCREQ Register */
__IO
uint32_t
buretvec
;
/**< <tt>\b 0x48:</tt> PWRSEQ BURETVEC Register */
__IO
uint32_t
buaod
;
/**< <tt>\b 0x4C:</tt> PWRSEQ BUAOD Register */
}
mxc_pwrseq_regs_t
;
/* Register offsets for module PWRSEQ */
...
...
@@ -119,18 +113,12 @@ typedef struct {
#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL)
/**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */
#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */
#define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */
#define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */
#define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL)
/**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */
#define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */
#define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */
#define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
#define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0044</tt> */
#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL)
/**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
#define MXC_R_PWRSEQ_LPMCSTAT ((uint32_t)0x00000050UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0050</tt> */
#define MXC_R_PWRSEQ_LPMCREQ ((uint32_t)0x00000054UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0054</tt> */
#define MXC_R_PWRSEQ_BURETVEC ((uint32_t)0x00000048UL)
/**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
#define MXC_R_PWRSEQ_BUAOD ((uint32_t)0x0000004CUL)
/**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
/**@} end of group pwrseq_registers */
/**
...
...
@@ -150,24 +138,9 @@ typedef struct {
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL)
/**< LPCN_RAMRET_EN3 Value */
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS)
/**< LPCN_RAMRET_EN3 Setting */
#define MXC_F_PWRSEQ_LPCN_OVR_POS 4
/**< LPCN_OVR Position */
#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS))
/**< LPCN_OVR Mask */
#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL)
/**< LPCN_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS)
/**< LPCN_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL)
/**< LPCN_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS)
/**< LPCN_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL)
/**< LPCN_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS)
/**< LPCN_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6
/**< LPCN_BLKDET Position */
#define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS))
/**< LPCN_BLKDET Mask */
#define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7
/**< LPCN_FVDDEN Position */
#define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS))
/**< LPCN_FVDDEN Mask */
#define MXC_F_PWRSEQ_LPCN_RREGEN_POS 8
/**< LPCN_RREGEN Position */
#define MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS))
/**< LPCN_RREGEN Mask */
#define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9
/**< LPCN_BCKGRND Position */
#define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS))
/**< LPCN_BCKGRND Mask */
...
...
@@ -177,11 +150,11 @@ typedef struct {
#define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11
/**< LPCN_BGOFF Position */
#define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS))
/**< LPCN_BGOFF Mask */
#define MXC_F_PWRSEQ_LPCN_V
DDC
MD_POS
20
/**< LPCN_V
DDC
MD Position */
#define MXC_F_PWRSEQ_LPCN_V
DDC
MD
((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_V
DDC
MD_POS))
/**< LPCN_V
DDC
MD Mask */
#define MXC_F_PWRSEQ_LPCN_V
CORE
MD_POS 20
/**< LPCN_V
CORE
MD Position */