1. 17 Apr, 2019 3 commits
  2. 11 Jan, 2019 1 commit
  3. 21 Aug, 2018 1 commit
  4. 23 Jul, 2018 1 commit
  5. 18 Jul, 2018 1 commit
    • Edward Fewell's avatar
      flash/nor: add support for TI MSP432 devices · 3e84da55
      Edward Fewell authored
      
      
      Added msp432 flash driver to support the TI MSP432P4x and
      MSP432E4x microcontrollers. Implemented the flash algo
      helper as used in the TI debug and flash tools. This
      implemention supports the MSP432E4, Falcon, and Falcon 2M
      variants. The flash driver automatically detects the
      connected variant and configures itself appropriately.
      Added command to mass erase device for consistency with
      TI tools and added command to unlock the protected BSL
      region.
      
      Tested using MSP432E401Y, MSP432P401R, and MSP432P4111
      LaunchPads.
      Tested with embedded XDS110 debug probe in CMSIS-DAP
      mode and with external SEGGER J-Link probe.
      
      Removed ti_msp432p4xx.cfg file made obsolete by this
      patch.
      Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0
      Signed-off-by: default avatarEdward Fewell <efewell@ti.com>
      Reviewed-on: http://openocd.zylin.com/4153
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarMatthias Welwarsky <matthias@welwarsky.de>
      Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
      3e84da55
  6. 15 Jun, 2018 1 commit
  7. 06 Jun, 2018 1 commit
    • Edward Fewell's avatar
      flash/nor: Add support for TI CC3220SF internal flash · d02de3a8
      Edward Fewell authored
      
      
      Added cc3220sf flash driver to support the TI CC3220SF
      microcontrollers. Implemented flash driver to support the
      internal flash of the CC3220SF. The implementation does not
      support the serial flash of the CC32xx family that requires
      connection over UART, and not via JTAG/SWD debug. Added config
      files for both CC32xx devices (no flash) and CC3220SF (with
      flash).
      
      Updated to implement comments from code review.
      Additional updates to handle remaining comments from review.
      Additional updates per review.
      
      Added code to only request aligned writes and full 32-bit
      words down to flash helper algorithm. Updated for recent
      changes in OpenOCD flash code.
      
      Removed cc32xx.cfg file made obsolete by this patch.
      Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47
      Signed-off-by: default avatarEdward Fewell <efewell@ti.com>
      Reviewed-on: http://openocd.zylin.com/4319
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
      d02de3a8
  8. 23 Apr, 2018 1 commit
  9. 07 Mar, 2018 1 commit
  10. 13 Jan, 2018 1 commit
    • Robert Jordens's avatar
      jtagspi: new protocol that includes transfer length · 867bdb2e
      Robert Jordens authored
      This commit contains a rewrite of the jtagspi protocol and covers both
      changes in the jtagspi.c openocd driver and the bscan_spi
      (xilinx_bscan_spi) proxy bitstreams. The changes are as follows:
      
      1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
      2. Insert alignment cycles for all BYPASSed TAPs:
      
        The previous logic was erroneous. The delay in clock cyles from a bit
        written to the jtag interface to a bit read by the jtag interface is:
      
        * The number of BYPASSed TAPs before this (jtagspi) tap
        * The length of the jtagspi data register (1)
        * The number of BYPASSed TAPs before this one.
      
        I.e. it is just the number of enabled TAPs. This also gets rid of the
        configuration parameter DR_LENGTH.
      
      3. Use marker bit to start spi transfer
      
        If there are TAPs ahead of this one on the JTAG chain, and we are in
        DR-SHIFT, there will be old bits toggled through first before the first
        valid bit destined for the flash.
        This delays the begin of the JTAGSPI transaction until the first high bit.
      
      4. New jtagspi protocol
      
        A JTAGSPI transfer now consists of:
      
        * an arbitrary number of 0 bits (from BYPASS registers in front of the
          JTAG2SPI DR)
        * a marker bit (1) indicating the start of the JTAG2SPI transaction
        * 32 bits (big endian) describing the length of the SPI transaction
        * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
        * an arbitrary number of cycles (to shift MISO/TDO data through
          subsequent BYPASS registers)
      
      5. xilinx_bscan_spi: clean up, add ultrascale
      
      This is tested on the following configurations:
      
      * KC705: XC7K325T
      * Sayma AMC: XCKU040
      * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
        adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
        Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
      
      
      * Custom board with Lattice FPGA + XC7A35T
      * CUstom board with 3x XCKU115-2FLVA1517E
      
      Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
      Signed-off-by: default avatarRobert Jordens <jordens@gmail.com>
      Reviewed-on: http://openocd.zylin.com/4236
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarPaul Fertser <fercerpav@gmail.com>
      867bdb2e
  11. 06 Dec, 2017 1 commit
  12. 03 Oct, 2017 1 commit
  13. 24 Apr, 2017 1 commit
  14. 04 Nov, 2016 1 commit
  15. 04 Oct, 2016 1 commit
  16. 14 Aug, 2016 1 commit
  17. 13 Aug, 2016 1 commit
  18. 20 May, 2016 1 commit
  19. 05 May, 2016 1 commit
  20. 04 May, 2016 4 commits
  21. 29 Feb, 2016 1 commit
    • Andreas Färber's avatar
      flash: New Spansion FM4 flash driver · 43ff5acd
      Andreas Färber authored
      
      
      The Spansion FM4 family of microcontrollers does not offer a way to
      identify the chip model nor the flash size, except for Dual Flash vs.
      regular layout. Therefore the family is passed as argument and
      wildcard-matched - MB9BFx6x and S6E2CC families are supported.
      
      Iterations showed that ...
      1) Just doing the flash command sequence from SRAM loader code for each
      half-word took 20 minutes for an 8 KB block.
      2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
      3) Significant performance gains were achieved by looping in loader code
      rather than in OpenOCD and by maximizing the batch size across sectors,
      getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
      (Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
      
      gcc, objcopy -Obinary and bin2char.sh are used for automating the
      integration of hand-written assembler snippets.
      
      Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
      Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      Reviewed-on: http://openocd.zylin.com/2190
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      43ff5acd
  22. 26 Nov, 2015 1 commit
  23. 30 Oct, 2015 2 commits
  24. 06 Aug, 2015 1 commit
    • Robert Jordens's avatar
      flash/nor/jtagspi: add JTAGSPI driver · d2535547
      Robert Jordens authored
      
      
      Many FPGA board speak JTAG and have a SPI flash for their bitstream
      attached to them. The SPI flash is programmed by first uploading a
      proxy bitstream to the FPGA that connects the JTAG interface to the
      SPI interface if the IR contains a certain USER instruction. Then the
      SPI flash can be erase, written, read directly through the JTAG DR.
      
      The JTAG and SPI signaling is compatible. Such a proxy bitstream only
      needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
      chip select when the IR contains the special instruction and the JTAG
      state machine is in the DR-SHIFT state.
      
      Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
      Signed-off-by: default avatarRobert Jordens <jordens@gmail.com>
      Reviewed-on: http://openocd.zylin.com/2844
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      d2535547
  25. 11 Feb, 2015 2 commits
  26. 24 Nov, 2014 1 commit
    • Anders's avatar
      flash/nor/lpcspifi.c: fix bug that prevented clean reset after flash write · 1662c854
      Anders authored
      
      
      After SPI flash was written by the assembly language stub,
      the last SPI command was not terminated by raising CS.
      This left the SPI device in a hung state that prevented the
      flash from being read by the M4 SPIFI controller, even after
      the M4 was fully reset. To access the flash via SPIFI, it was
      necessary to completely power cycle the board.
      
      This fix adds the missing instructions to raise CS and
      terminate the SPI command after the last byte. This allows
      the M4 to be resumed or reset cleanly after flashing. The
      SPIFI memory is now immediately accessable at address
      0x1400 0000 after flashing is complete.
      
      Change-Id: I4d5e03bded0fa00c430c2991f182dc18611d5f48
      Signed-off-by: default avatarAnders <anders@openpuma.org>
      Reviewed-on: http://openocd.zylin.com/2359
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      1662c854
  27. 22 Sep, 2014 1 commit
  28. 29 Mar, 2014 1 commit
  29. 07 Aug, 2013 1 commit
    • Paul Fertser's avatar
      mdr32fx: support for Milandr's MDR32Fx internal flash memory · fccc5522
      Paul Fertser authored
      
      
      This adds example config and flash driver for russian Cortex-M3
      microcontroller model.
      
      Run-time tested on MDR32F9Q2I evaluation board; the flash driver
      should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware
      to test.
      
      There're no status bits at all, the datasheets specifies some delays
      for flash operations instead. All being in <100us range, they're hard
      to violate with JTAG, I hope. There're also no flash identification
      registers so the flash size and type has to be hardcoded into the
      config.
      
      The flashing is considerably complicated because the flash is split
      into pages, and each page consists of 4 interleaved non-consecutive
      "sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the
      fastest way is to latch the page and sector address and then write
      only the part that should go into the current page and current sector.
      
      Performance testing results with adapter_khz 1000 and the chip running
      on its default HSI 8MHz oscillator:
      
      When working area is specified, a target helper algorithm is used:
      wrote 131072 bytes from file testfile.bin in 3.698427s (34.609 KiB/s)
      
      This can theoretically be sped up by ~1.4 times if the helper
      algorithm is fed some kind of "loader instructions stream" to allow
      sector-by-sector writing.
      
      Pure JTAG implementation (when target memory area is not available)
      flashes all the 128k memory in 49.5s.
      
      Flashing "info" memory region is also implemented, but due to the
      overlapping memory addresses (resulting in incorrect memory map
      calculations for GDB) it can't be used at the same time, so OpenOCD
      needs to be started this way: -c "set IMEMORY true" -f
      target/mdr32f9q2i.cfg
      
      It also can't be read/verified because it's not memory-mapped anywhere
      ever, and OpenOCD NOR framework doesn't really allow to provide a
      custom handler that would be used when verifying.
      
      Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316
      Signed-off-by: default avatarPaul Fertser <fercerpav@gmail.com>
      Reviewed-on: http://openocd.zylin.com/1532
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      fccc5522
  30. 01 Jul, 2013 1 commit
  31. 05 Jun, 2013 1 commit
  32. 02 Apr, 2013 1 commit
  33. 14 Jan, 2013 1 commit