1. 17 Apr, 2019 3 commits
  2. 04 Apr, 2019 1 commit
  3. 11 Jan, 2019 1 commit
  4. 06 Dec, 2018 2 commits
  5. 25 Sep, 2018 1 commit
  6. 07 Sep, 2018 1 commit
  7. 21 Aug, 2018 1 commit
  8. 23 Jul, 2018 1 commit
  9. 18 Jul, 2018 1 commit
    • Edward Fewell's avatar
      flash/nor: add support for TI MSP432 devices · 3e84da55
      Edward Fewell authored
      Added msp432 flash driver to support the TI MSP432P4x and
      MSP432E4x microcontrollers. Implemented the flash algo
      helper as used in the TI debug and flash tools. This
      implemention supports the MSP432E4, Falcon, and Falcon 2M
      variants. The flash driver automatically detects the
      connected variant and configures itself appropriately.
      Added command to mass erase device for consistency with
      TI tools and added command to unlock the protected BSL
      Tested using MSP432E401Y, MSP432P401R, and MSP432P4111
      Tested with embedded XDS110 debug probe in CMSIS-DAP
      mode and with external SEGGER J-Link probe.
      Removed ti_msp432p4xx.cfg file made obsolete by this
      Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0
      Signed-off-by: default avatarEdward Fewell <efewell@ti.com>
      Reviewed-on: http://openocd.zylin.com/4153
      Tested-by: jenkins
      Reviewed-by: default avatarMatthias Welwarsky <matthias@welwarsky.de>
      Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
  10. 15 Jun, 2018 1 commit
  11. 06 Jun, 2018 1 commit
    • Edward Fewell's avatar
      flash/nor: Add support for TI CC3220SF internal flash · d02de3a8
      Edward Fewell authored
      Added cc3220sf flash driver to support the TI CC3220SF
      microcontrollers. Implemented flash driver to support the
      internal flash of the CC3220SF. The implementation does not
      support the serial flash of the CC32xx family that requires
      connection over UART, and not via JTAG/SWD debug. Added config
      files for both CC32xx devices (no flash) and CC3220SF (with
      Updated to implement comments from code review.
      Additional updates to handle remaining comments from review.
      Additional updates per review.
      Added code to only request aligned writes and full 32-bit
      words down to flash helper algorithm. Updated for recent
      changes in OpenOCD flash code.
      Removed cc32xx.cfg file made obsolete by this patch.
      Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47
      Signed-off-by: default avatarEdward Fewell <efewell@ti.com>
      Reviewed-on: http://openocd.zylin.com/4319
      Tested-by: jenkins
      Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
  12. 31 May, 2018 1 commit
    • Edward Fewell's avatar
      jtag/drivers: Add support for TI XDS110 debug probe · 2ba27e2f
      Edward Fewell authored
      Add support for the XDS110 debug probe using the APIs in the
      probe's firmware. Includes support for older versions of the
      firmware (with reduced performance) and support for a newer
      version that includes OpenOCD specific APIs. Tested on various
      TI LauchPads including MSP432P4, MSP432E4, CC2650, CC2652, and
      Updated to add better support for swd switch. Removed issues found with
      clang static analysis.
      Updated to add rules entry for the XDS110 probe and Tiva DFU mode (which
      affects both XDS110 and ICDI probes).
      Change-Id: Ib274143111a68e67e80003797c6a68e3e80976b2
      Signed-off-by: default avatarEdward Fewell <efewell@ti.com>
      Reviewed-on: http://openocd.zylin.com/4322
      Tested-by: jenkins
      Reviewed-by: default avatarMatthias Welwarsky <matthias@welwarsky.de>
  13. 23 Apr, 2018 1 commit
  14. 10 Apr, 2018 1 commit
    • Tomas Vanek's avatar
      target armv7m: multi-block erase check · a867e36f
      Tomas Vanek authored
      Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode,
      Plain read:
      	flash read_bank 0 /dev/null
      takes 48 seconds.
      erase_check without this change:
      	flash erase_check 0
      takes horrible 149 seconds!!
      And the same command with the change applied takes 1.8 seconds.
      Quite a difference.
      Remove the erase-value=0 version of algorithm as the new one can check
      for any value.
      If the target is an insane slow clocked CPU (under 1MHz) algo
      timeouts. Blocks checked so far are returned and the next call
      uses increased timeout.
      Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd
      Signed-off-by: default avatarTomas Vanek <vanekt@fbl.cz>
      Reviewed-on: http://openocd.zylin.com/4298
      Tested-by: jenkins
      Reviewed-by: default avatarJonas Norling <jonas.norling@cyanconnode.com>
      Reviewed-by: default avatarAndreas Bolsch <hyphen0break@gmail.com>
  15. 07 Mar, 2018 1 commit
  16. 13 Jan, 2018 2 commits
    • Robert Jordens's avatar
      jtagspi: new protocol that includes transfer length · 867bdb2e
      Robert Jordens authored
      This commit contains a rewrite of the jtagspi protocol and covers both
      changes in the jtagspi.c openocd driver and the bscan_spi
      (xilinx_bscan_spi) proxy bitstreams. The changes are as follows:
      1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
      2. Insert alignment cycles for all BYPASSed TAPs:
        The previous logic was erroneous. The delay in clock cyles from a bit
        written to the jtag interface to a bit read by the jtag interface is:
        * The number of BYPASSed TAPs before this (jtagspi) tap
        * The length of the jtagspi data register (1)
        * The number of BYPASSed TAPs before this one.
        I.e. it is just the number of enabled TAPs. This also gets rid of the
        configuration parameter DR_LENGTH.
      3. Use marker bit to start spi transfer
        If there are TAPs ahead of this one on the JTAG chain, and we are in
        DR-SHIFT, there will be old bits toggled through first before the first
        valid bit destined for the flash.
        This delays the begin of the JTAGSPI transaction until the first high bit.
      4. New jtagspi protocol
        A JTAGSPI transfer now consists of:
        * an arbitrary number of 0 bits (from BYPASS registers in front of the
          JTAG2SPI DR)
        * a marker bit (1) indicating the start of the JTAG2SPI transaction
        * 32 bits (big endian) describing the length of the SPI transaction
        * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
        * an arbitrary number of cycles (to shift MISO/TDO data through
          subsequent BYPASS registers)
      5. xilinx_bscan_spi: clean up, add ultrascale
      This is tested on the following configurations:
      * KC705: XC7K325T
      * Sayma AMC: XCKU040
      * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
        adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
        Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
      * Custom board with Lattice FPGA + XC7A35T
      * CUstom board with 3x XCKU115-2FLVA1517E
      Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
      Signed-off-by: default avatarRobert Jordens <jordens@gmail.com>
      Reviewed-on: http://openocd.zylin.com/4236
      Tested-by: jenkins
      Reviewed-by: default avatarPaul Fertser <fercerpav@gmail.com>
    • Aleksey Shargalin's avatar
      remote_bitbang_sysfsgpio: fix reset handling · b34e0139
      Aleksey Shargalin authored
      When both SRST and TRST asserted, 'u' is sent to remote bitbang.
      Fix for correct handling of such a case
      Change-Id: I2a93ff71f5bbae658e6c0c3649a9fbcca2c5a14b
      Signed-off-by: default avatarAleksey Shargalin <myokaski@gmail.com>
      Reviewed-on: http://openocd.zylin.com/4283
      Tested-by: jenkins
      Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
  17. 07 Dec, 2017 1 commit
  18. 06 Dec, 2017 1 commit
  19. 03 Oct, 2017 1 commit
  20. 17 Jun, 2017 1 commit
  21. 12 May, 2017 1 commit
  22. 24 Apr, 2017 2 commits
  23. 25 Dec, 2016 1 commit
  24. 08 Dec, 2016 2 commits
  25. 04 Nov, 2016 1 commit
  26. 04 Oct, 2016 1 commit
  27. 14 Aug, 2016 1 commit
  28. 13 Aug, 2016 2 commits
  29. 22 May, 2016 3 commits
  30. 20 May, 2016 1 commit
  31. 17 May, 2016 1 commit