1. 30 Aug, 2011 1 commit
  2. 24 Aug, 2011 1 commit
  3. 17 Aug, 2011 1 commit
  4. 12 Aug, 2011 3 commits
  5. 10 Aug, 2011 2 commits
    • Rodrigo L. Rosa's avatar
      fix return code from dsp5680xx_read · 7675db7e
      Rodrigo L. Rosa authored
      it returned ERROR_OK even though it actually failed.
      this made the Tcl interface report success, though it had not succeeded.
      7675db7e
    • Rodrigo L. Rosa's avatar
      renamed for clarity · 67f1f0c7
      Rodrigo L. Rosa authored
      i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
      i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
      67f1f0c7
  6. 09 Aug, 2011 9 commits
    • Drasko DRASKOVIC's avatar
      mips32 : Fixed memory byte access · 827057f5
      Drasko DRASKOVIC authored
      Function mips_m4k_write_memory() does endianess byte swap,
      but this procedure break one byte access (temporary array
      overwrites content in buffer).
      As a fix, this endianess swap and buffer affecting
      is preformed only on hword and word accesses (not on byte access).
      827057f5
    • Drasko DRASKOVIC's avatar
      mips32: Sync Caches to Make Instr Writes Effective · c18e0238
      Drasko DRASKOVIC authored
      Pprogram that loads another program into memory is actually writing the
      D- side cache.
      The instructions it has loaded can't be executed until they reach the
      I-cache.
      
      After the instructions have been written, the loader should arrange to
      write back any containing D-cache line and invalidate any locations
      already in the I-cache.
      
      For the MIPS Architecture Release2 cores, we can use synci command
      that does this job.
      For Release1 we must use "cache" instruction.
      c18e0238
    • Drasko DRASKOVIC's avatar
      mips32: Added CP0 coprocessor R/W routines · 1be71634
      Drasko DRASKOVIC authored
      This patch adds MIPS32 CP0 coprocessor R/W routines,
      as well as adequate commands to use these routines via
      telnet interface.
      
      Now is becomes possible to affect CP0 internal registers
      and configure CPU directly from OpenOCD.
      1be71634
    • Drasko DRASKOVIC's avatar
      mips_m4k: common_magic should be unsigned · 800bc930
      Drasko DRASKOVIC authored
      For all architectures we use distinct common magic number,
      and this should be a uint32_t type.
      Otherwise, comparison with macros will yield compilation
      warning.
      800bc930
    • Drasko DRASKOVIC's avatar
      mips32: Removed Unnecessary JTAG Queue Flush · e1466df5
      Drasko DRASKOVIC authored
      jtag_execute_queue() is executed as a part of mips_ejtag_drscan_32().
      No need for this to be done before - removed for optimisation.
      e1466df5
    • Øyvind Harboe's avatar
      Revert "dsp5680xx: disable for now, it generates warnings" · 7d2bf880
      Øyvind Harboe authored
      This reverts commit d567df02.
      7d2bf880
    • Rodrigo L. Rosa's avatar
      dsp5680xx fix constante ref · c2c19c50
      Rodrigo L. Rosa authored
      a counter was incorrectly set
      when i added the macros i incorrectly called them.
      fixed that.
      c2c19c50
    • Rodrigo L. Rosa's avatar
      dsp5680xx fix FM clk · e8543de8
      Rodrigo L. Rosa authored
      before doing anything with the flash module (FM) the clock divider must be set.
      if erase_check was the first thing done with the FM after reset then an error would be generated because the clk divider was not set.
      now erase_check sets the clk divider.
      e8543de8
    • Rodrigo L. Rosa's avatar
      dps5680xx fix warnings · ba68ae8b
      Rodrigo L. Rosa authored
      reorganized code to get rid of compiler warnings
      the warning were related to allignment, i do not get these warning on my build system (i've tried setting the compiler flag but it doesn't work, still working on why) so i cannot detect them (yet.)
      ba68ae8b
  7. 08 Aug, 2011 1 commit
  8. 01 Aug, 2011 1 commit
  9. 04 Jul, 2011 3 commits
    • Drasko DRASKOVIC's avatar
      mips_m4k and arm7_9 : Fix soft bkpt endianess for 16-bit instructions · ac43d7a6
      Drasko DRASKOVIC authored
      The patch fix comparison of target data on the host by using
      target_buffer_get_u16() to transform current_instr to
      _host_ endianess before comparison.
      ac43d7a6
    • Peter Horn's avatar
      cortex_m3: add auto maskisr · d4cd6f03
      Peter Horn authored
      
      
      This patch extends the cortex_m3 maskisr command by a new option 'auto'.
      The 'auto' option handles interrupts during stepping in a way they are
      processed but don't disturb the program flow during debugging.
      
      Before one had to choose to either enable or disable interrupts. The former
      steps into interrupt handlers when they trigger. This disturbs the flow during
      debugging, making it hard to follow some piece of code when interrupts occur
      often.
      
      When interrupts are disabled, the flow isn't disturbed but code relying on
      interrupt handlers to be processed will stop working. For example a delay
      function counting the number of timer interrupts will never complete, RTOS
      task switching will not occur and output I/O queues of interrupt driven
      I/O will stall or overflow.
      
      Using the 'maskisr' command also typically requires gdb hooks to be supplied
      by the user to switch interrupts off during the step and to enable them again
      afterward.
      
      The new 'auto' option of the 'maskisr' command solves the above problems. When
      set, the step command allows pending interrupt handlers to be executed before
      the step, then the step is taken with interrupts disabled and finally interrupts
      are enabled again. This way interrupt processing stays in the background without
      disturbing the flow of debugging. No gdb hooks are required. The 'auto'
      option is the default, since it's believed that handling interrupts in this
      way is suitable for most users.
      
      The principle used for interrupt handling could probably be used for other
      targets too.
      Signed-off-by: default avatarSpencer Oliver <ntfreak@users.sourceforge.net>
      d4cd6f03
    • Spencer Oliver's avatar
      Revert "cortex_m3: add auto maskisr" · 89fa8ce2
      Spencer Oliver authored
      This reverts commit ff640f19.
      
      Original patch reverted as Author's name was incorrectly set.
      89fa8ce2
  10. 01 Jul, 2011 1 commit
    • Drasko DRASKOVIC's avatar
      mips_m4k : Fix soft breakpoint endianess handling · bad3ee87
      Drasko DRASKOVIC authored
      In order to compare data read from the target with some marcros or data
      defined on the host, we must transform this read data from target
      endianess to host endianess.
      target_read_memory() gets bytes from target to the host, but keeps them in _target_
      endianess. This is OK if we just want to temporary keep this data on the
      host, like keeping breakpoint->orig_instr. But if we want to use this
      data for any ispections and comparisons on the host side, we must
      transform it to _host_ endianess, by using target_buffer_get_u32()
      function.
      Currently this transformation is missing, and check current_instr ==
      MIPS32_SDBBP will never pass if target and host endianess differ,
      because current_instr will be kept in _target_ endianess and
      MIPS32_SDBBP will be kept in _host_ endianess,
      
      The patch fix this issue by using target_buffer_get_u32() to transform current_instr to
      _host_ endianess before comparison.
      bad3ee87
  11. 28 Jun, 2011 5 commits
    • Øyvind Harboe's avatar
      dsp5680xx: disable for now, it generates warnings · d567df02
      Øyvind Harboe authored
      Use "git revert <commit>" to revert this commit, then build and
      repair and post patch to the mailing list.
      
      Warnings generated with:
      
      nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
      
      openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
      openocd/src/target/dsp5680xx.c:252: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
      openocd/src/target/dsp5680xx.c:268: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
      openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
      pointer will break strict-aliasing rules
      openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
      openocd/src/target/dsp5680xx.c:736: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c:737: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
      openocd/src/target/dsp5680xx.c:823: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
      openocd/src/target/dsp5680xx.c:938: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c:941: warning: cast increases required
      alignment of target type
      openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
      openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
      alignment of target type
      d567df02
    • Øyvind Harboe's avatar
      mips4k: fix big-endian hosts and host alignment problems · 2482244b
      Øyvind Harboe authored
      the code was making assumptions about the endianness of the host.
      2482244b
    • Øyvind Harboe's avatar
      dsp5680xx: fix compilation problems · e4c054ca
      Øyvind Harboe authored
      use a more specific global variable name than "context", which
      can easily conflict with other things.
      e4c054ca
    • Spencer Oliver's avatar
      cortex_m3: add auto maskisr · ff640f19
      Spencer Oliver authored
      
      
      This patch extends the cortex_m3 maskisr command by a new option 'auto'.
      The 'auto' option handles interrupts during stepping in a way they are
      processed but don't disturb the program flow during debugging.
      
      Before one had to choose to either enable or disable interrupts. The former
      steps into interrupt handlers when they trigger. This disturbs the flow during
      debugging, making it hard to follow some piece of code when interrupts occur
      often.
      
      When interrupts are disabled, the flow isn't disturbed but code relying on
      interrupt handlers to be processed will stop working. For example a delay
      function counting the number of timer interrupts will never complete, RTOS
      task switching will not occur and output I/O queues of interrupt driven
      I/O will stall or overflow.
      
      Using the 'maskisr' command also typically requires gdb hooks to be supplied
      by the user to switch interrupts off during the step and to enable them again
      afterward.
      
      The new 'auto' option of the 'maskisr' command solves the above problems. When
      set, the step command allows pending interrupt handlers to be executed before
      the step, then the step is taken with interrupts disabled and finally interrupts
      are enabled again. This way interrupt processing stays in the background without
      disturbing the flow of debugging. No gdb hooks are required. The 'auto'
      option is the default, since it's believed that handling interrupts in this
      way is suitable for most users.
      
      The principle used for interrupt handling could probably be used for other
      targets too.
      Signed-off-by: default avatarSpencer Oliver <ntfreak@users.sourceforge.net>
      ff640f19
    • Peter Horn's avatar
      e53f7e5f
  12. 24 Jun, 2011 1 commit
    • Drasko DRASKOVIC's avatar
      Fix load_image for ELF with all p_paddr set to zero · 37aaa282
      Drasko DRASKOVIC authored
      So far image_load command tries to load ELF binaries to address
      discovered by reading p_paddr member of a Program header of an ELF
      segment.
      
      However, ELF specifications says for p_paddr : ...Because System V
      ignores physical addressing for application programs, this member has
      unspecified contents for executable files and shared objects.
      
      ARM ELF specifiaction goes even further, demanding that this member
      be set to zero, using the p_vaddr as a segment load address.
      
      To avoid the cases to wrong addr where p_paddr is zero,
      we are now using p_vaddr to as a load destination in case that *all*
      p_paddr == 0. Basically, this patch re-implements the approach present in
      BDF's elf.c, which is used by GDB also (so that we can be consistent).
      37aaa282
  13. 17 Jun, 2011 2 commits
  14. 13 Jun, 2011 1 commit
  15. 12 Jun, 2011 8 commits