1. 18 Aug, 2009 6 commits
  2. 16 Aug, 2009 5 commits
  3. 13 Aug, 2009 1 commit
  4. 07 Aug, 2009 4 commits
  5. 06 Aug, 2009 3 commits
  6. 31 Jul, 2009 1 commit
  7. 27 Jul, 2009 2 commits
  8. 26 Jul, 2009 4 commits
  9. 24 Jul, 2009 3 commits
  10. 23 Jul, 2009 4 commits
  11. 22 Jul, 2009 2 commits
  12. 21 Jul, 2009 4 commits
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · d460a7cd
      ntfreak authored
      Dump SP on poll, and show whether it's MSP or PSP.
      
      Thread mode can use either stack pointer, so this is
      part of the state that's not yet displayed.
      
      Shrink some lines.
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      d460a7cd
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · 4da019ed
      ntfreak authored
      Clean up treatment of registers in ARMv7-M and Cortex-M3. 
      
       - At the arch level:
          * Just list registers and names; don't impose core-specific
            policy about how they are accessed.
          * Each register has a symbol.
          * Remove the register mode field (irrelevant to debugger)
      
       - At the core/implementation level:
          * Just map the registers to their relevant access methods;
            don't require the arch level to say how that should work
            (cores other than Cortex-M3 could do it differently).
          * Don't use undefined bits from register 20.
          * Use register IDs that are part of the ARMv7-M interface.
      
      In short, there's now a real distinction between the arch
      and core layers.
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      4da019ed
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · eea04862
      ntfreak authored
      Minor updates to the Thumb2 disassembly:
      
       - Bugfixes:
          * Distinguish branch from misc via "!=" not "=="
          * MRS register shift is 8 bits (vs MSR being 16)
       - Format tweaks:
          * CPS needed tab (not space)
          * add commma before some shifts
          * add space after comma in LDM/STM
          * use ".W" width spec on various instructions
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      eea04862
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · cd0ca916
      ntfreak authored
      Revert parts of the previous ARMv7-M register patch.
      It turns out that part of the issue is a documentation
      problem for the Cortex-M3 r1 parts. So for the rest,
      simpler fixes are possible (in followup patch).
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      cd0ca916
  13. 20 Jul, 2009 1 commit