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    • Olivier Schonken's avatar
      topic: Added support for the SAM4S variants · d1cd9777
      Olivier Schonken authored
      
      
      Atmel introduced 6 new Cortex-M4 processors on 2011-10-26
      SAM4S16C - 1024KB flash LQFP100/BGA100
      SAM4S16B - 1024KB flash LQFP64/QFN64
      SAM4S16A - 1024KB flash LQFP48/QFN48
      SAM4S8C - 512KB flash LQFP100/BGA100
      SAM4S8B - 512KB flash LQFP64/QFN64
      SAM4S8A - 512KB flash LQFP48/QFN48
      
      The SAM4S processors still suffer from the "6 waitstates needed
      to program device" errata.
      
      Other relevant changes are:
      1. Address of flash memory starts at 0x400000.
      2. EWP (Erase page and write page) only works for the first two 8KB "sectors"
      3. Because of the EWP not working for all the sectors, normal page writes have
      to be used.  The default_flash_blank_check is used to check if lockregions
      should be erased.
      4. The EA (Erase All) command takes 7.3s to complete. (Previous timeout was
      500 ms)
      5. There are 128 lockable regions of 8KB each.
      
      Implemented default blank checking, and page erase for load_image scenarios.
      This is to compensate for the EWP flash commands only working on the
      first 2 8KB sectors.
      
      Change-Id: I7c5a52b177f7849a107611fd0f635fc416cfb724
      Signed-off-by: default avatarOlivier Schonken <olivier.schonken@gmail.com>
      Reviewed-on: http://openocd.zylin.com/528
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      d1cd9777
  32. 13 Mar, 2012 1 commit
    • Olivier Schonken's avatar
      topic: Added support for the SAM3X/A variants · 736e8bb7
      Olivier Schonken authored
      
      
      Atmel introduced 7 new Cortex-M3 processors on 2012-02-28
      SAM3X4C - 256KB flash
      SAM3X4E - 256KB flash
      SAM3X8C - 512KB flash
      SAM3X8E - 512KB flash
      SAM3X8H (Only on dev-kit - not in production...) - 512KB flash
      SAM3A4C - 256KB flash
      SAM3A8C - 256KB flash
      
      The SAM3X/A processors still suffer from the "6 waitstates needed
      to program device" errata.
      
      The CIDR address for the SAM3X/A processors are different from the
      other SAM3 processors.  Unfortunately, the chip identification register
      is not at a constant address across all of the SAM3 series'. As a
      consequence, a simple heuristic is used to find where it's
      at... If the contents at the first address is zero, then we know
      that the second address is where the chip id register is.
      We can deduce this because for those SAM's that have the chip id @ 0x400e0940,
      the first address, 0x400e0740, is located in the memory map of the Power
      Management Controller (PMC). Furthermore, the address is not used by the PMC.
      So when read, the memory controller returns zero.
      
      Another interesting change is the flash bank address for flash bank 1.
      It is not fixed at 0x00100000 like the Sam3U.  Bank 1 of the at91sam3a/x
      series starts at 0x00080000 + half the total flash size.  Thus for the 256KB
      devices Bank 1 is located at 0x000A0000, and for the 512KB devices Bank 1 is
      located at 0x000C0000.
      
      The configuration files for the SAM3X/A processors will follow
      
      Change-Id: I6c3a707c00e05d993a2ad1d5a423f23b37ffd553
      Signed-off-by: default avatarOlivier Schonken <olivier.schonken@gmail.com>
      Reviewed-on: http://openocd.zylin.com/505
      
      
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      736e8bb7
  33. 06 Mar, 2012 2 commits