1. 01 Mar, 2010 4 commits
  2. 28 Feb, 2010 13 commits
  3. 27 Feb, 2010 4 commits
    • David Brownell's avatar
      new "stellaris recover" command · e70d42a7
      David Brownell authored
      
      
      Stellaris chips have a procedure for restoring the chip to
      what's effectively the "as-manufactured" state, with all the
      non-volatile memory erased.  That includes all flash memory,
      plus things like the flash protection bits and various control
      words which can for example disable debugger access.  clearly,
      this can be useful during development.
      
      Luminary/TI provides an MS-Windows utility to perform this
      procedure along with its Stellaris developer kits.  Now OpenOCD
      users will no longer need to use that MS-Windows utility.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      e70d42a7
    • David Brownell's avatar
      ADIv5 DAP ops switching to JTAG or SWD modes · 3ef9beb5
      David Brownell authored
      
      
      Define two new DAP operations which use the new jtag_add_tms_seq()
      calls to put the DAP's transport into either SWD or JTAG mode, when
      the hardware allows.
      
      Tested with the Stellaris 'Recovering a "Locked" Device' procedure,
      which loops five times over both of these.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      3ef9beb5
    • David Brownell's avatar
      ft2232: implement TMS sequence command · 8c9b52e8
      David Brownell authored
      
      
      Implement the new TMS_SEQ command on FT2232 hardware.
      Also, swap a bogus exit() call with a clean failure return.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      8c9b52e8
    • David Brownell's avatar
      interface: define TMS sequence command · a3245bd7
      David Brownell authored
      
      
      For support of SWD we need to be able to clock out special bit
      sequences over TMS or SWDIO.  Create this as a generic operation,
      not yet called by anything, which is split as usual into:
      
       - upper level abstraction ... here, jtag_add_tms_seq();
       - midlayer implementation logic hooking that to the lowlevel code;
       - lowlevel minidriver operation ... here, interface_add_tms_seq();
       - message type for request queue, here JTAG_TMS.
      
      This is done slightly differently than other operations: there's a flag
      saying whether the interface driver supports this request.  (In fact a
      flag *word* so upper layers can learn about other capabilities too ...
      for example, supporting SWD operations.)
      
      That approach (flag) lets this method *eventually* be used to eliminate
      pathmove() and statemove() support from most adapter drivers, by moving
      all that logic into the mid-layer and increasing uniformity between the
      various drivers.  (Which will in turn reduce subtle bugginess.)
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a3245bd7
  4. 25 Feb, 2010 3 commits
    • Mariano Alvira's avatar
      ft2232: add a mechanism to specify channel in layout structs · 4a64820f
      Mariano Alvira authored
      
      
      FT2232-family chips have two or more MPSSE modules.   FTDI documentation
      calls these channels.  JTAG adapter drivers thus need to be able to choose
      which channel to use.  (For example, one channel may connect to a board's
      microcontroller, while another connects to a CPLD.)
      
      Since each channel has its own USB interface, libftdi (somewhat confusingly)
      identifies channels using INTERFACE_* symbols.  Most boards use INTERFACE_A
      for JTAG, which is the default in OpenOCD.  But some wire up a different one.
      
      Note that there are two facets of what makes a wiring "layout":
      
       - The mapping between debug signals map and channel signals ... embedded
         in C functions.
      
       - Label used in Tcl configuration scripts ... part of the "layout" structure.
      
      By letting the channel be part of the layout struct, we permit sharing the C
      functions between Tcl-visible layouts, when those signal mappings are reused.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      4a64820f
    • David Brownell's avatar
      ARM ADIv5 doxygen and cleanup · 79010bf3
      David Brownell authored
      
      
      Add doxygen for mem_ap_read_buf_u{8,16,32}() calls,
      and shrink a few overlong lines.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      79010bf3
    • Hans Peter Mortensn's avatar
      AVR flash: handle AT90CAN128 chips · 7abe9f38
      Hans Peter Mortensn authored
      
      
      I have successfully programmed the AT90CAN128, based on the mega128  
      with some small modifications.
      
      [ dbrownell@users.sourceforge.net: patch cleanup ]
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      7abe9f38
  5. 24 Feb, 2010 1 commit
  6. 22 Feb, 2010 5 commits
  7. 21 Feb, 2010 10 commits
    • David Brownell's avatar
      ADIv5: relocate memacess_tck cycles · c8ea748d
      David Brownell authored
      
      
      When using an AP to access a memory (or a memory-mapped register),
      some extra TCK (assuming JTAG) cycles should be added to ensure
      the AP has enugh time to complete that access before trying to
      collect the response.
      
      The previous code was adding these cycles *before* trying to
      access (read or write) data to that address, not *after*.  Fix
      by putting the delays in the right location.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      c8ea748d
    • David Brownell's avatar
      ADIv5: remove ATOMIC/COMPOSITE interface mode · 3b68a708
      David Brownell authored
      
      
      This removes context-sensitivity from the programming interface and makes
      it possible to know what a block of code does without needing to know the
      previous history (specifically, the DAP's "trans_mode" setting).
      
      The mode was only set to ATOMIC briefly after DAP initialization, making
      this patch be primarily cleanup; almost everything depends on COMPOSITE.
      The transactions which shouldn't have been queued were already properly
      flushing the queue.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      3b68a708
    • David Brownell's avatar
      ARM: ADIv5, deadcode cleanup · ecff7304
      David Brownell authored
      
      
      I have no idea what the scan_inout_check() was *expecting* to achieve by
      issuing a read of the DP_RDBUFF register.  But in any case, that code was
      clearly never being called ("invalue" always NULL) ... so remove it, and
      the associated comment.
      
      Also rename it as ap_write_check(), facilitating a cleanup of its single
      call site by removing constant parameters.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      ecff7304
    • David Brownell's avatar
      ARM: ADIv5 code shrinkage, cleanup · 39cfe627
      David Brownell authored
      
      
      adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing
      code duplication.  Include doxygen for the former.  Comment
      some particularly relevant points.  Minor fault handling fixes
      for both routines:  don't register a callback that can't run,
      or return ERROR_OK after an error.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      39cfe627
    • David Brownell's avatar
      ADIv5 clean up AP fault handling · a97bb675
      David Brownell authored
      
      
      Pass up fault codes from various routines, so their callers
      can clean up after failures, and remove the FIXME comments
      highlighting those previously goofy code paths.
      
       dap_ap_{read,write}_reg_u32()
       dap_ap_write_reg()
       mem_ap_{read,write}_u32()
       mem_ap_{read,write}_atomic_u32()
       dap_setup_accessport()
      
      Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(),
      instead of cloning its core code (and broken fault handling).
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a97bb675
    • David Brownell's avatar
      ADIv5 clean up AP selection and register caching · 249263d2
      David Brownell authored
      
      
      Handling of AP (and AP register bank) selection, and cached AP
      registers, is pretty loose ... start tightening it:
      
       - It's "AP bank" select support ... there are no DP banks.  Rename.
         + dap_dp_bankselect() becomes dap_ap_bankselect()
         + "dp_select_value" struct field becomes "ap_bank_value"
      
       - Remove duplicate AP cache init paths ... only use dap_ap_select(),
       and don't make Cortex (A8 or M3) cores roll their own code.
      
       - For dap_ap_bankselect(), pass up any fault code from writing
       the SELECT register.  (Nothing yet checks those codes.)
      
       - Add various bits of Doxygen
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      249263d2
    • David Brownell's avatar
      ARM: keep a handle to the PC · 1aac72d2
      David Brownell authored
      
      
      Keep a handle to the PC in "struct arm", and use it.
      This register is used a fair amount, so this is a net
      minor code shrink (other than some line length fixes),
      but mostly it's to make things more readable.
      
      For XScale, fix a dodgy sequence while stepping.  It
      was initializing a variable to a non-NULL value, then
      updating it to handle the step-over-active-breakpoint
      case, and then later testing for non-NULL to see if
      it should reverse that step-over-active logic.  It
      should have done like ARM7/ARM9 does: init to NULL.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      1aac72d2
    • David Brownell's avatar
      ARM DPM: support adding/removing HW breakpoints · a299371a
      David Brownell authored
      
      
      Generalize the core of watchpoint setup so that it can handle
      breakpoints too.  Create breakpoint add/remove routines which
      will use that, and hook them up to target types which don't
      provide their own breakpoint support (nothing, yet).
      
      This suffices for hardware-only breakpoint support.  The ARM11
      code will be able to switch over to this without much trouble,
      since it doesn't yet handle software breakpoints.  Switching
      Cortex-A8 will be a bit more involved.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a299371a
    • David Brownell's avatar
      ARM11: per-core options should not be global · 27c068c1
      David Brownell authored
      
      
      Address some FIXME comments by getting rid of globals, moving
      per-core parameters in the existing per-core data structure.
      
      This will matter most whenever there are multiple ARM11 cores,
      e.g. ARM11 MPcore chips, but in general is just cleanup.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      27c068c1
    • David Brownell's avatar
      ARMv7-M: start using "struct arm" · ce1feaa7
      David Brownell authored
      
      
      This sets up a few of the core "struct arm" data structures so they
      can be used with ARMv7-M cores.  Specifically, it:
      
       - defines new ARM core_modes to match the microcontroller modes
         (e.g. HANDLER not IRQ, and two types of thread mode);
      
       - Establishes a new microcontroller "core_type", which can be
         used to make sure v7-M (and v6-M) cores are handled right;
      
       - adds "struct arm" to "struct armv7m" and arranges for the
         target_to_armv7m() converter to use it;
      
       - sets up the arm.core_cache and arm.cpsr values
      
       - makes the Cortex-M3 code maintain arm.map and arm.core_mode.
      
      This is currently set up as a parallel data structure, primarily to
      minimize special cases for the semihosting support with microcontroller
      profile cores.
      
      Later patches can rip out the duplicative ARMv7-M support and start
      reusing core ARM code.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      ce1feaa7