1. 14 Mar, 2019 1 commit
  2. 31 Jul, 2018 1 commit
    • Oleksij Rempel's avatar
      mips_m4k: add optional reset handler · 16e95146
      Oleksij Rempel authored
      In some cases by using SRST we can't halt CPU early enough. And
      option PrRst is not available too. In this case the only way is
      to set BOOT flag over EJTAG and reset CPU or SoC from CPU itself.
      For example by writing to some reset register.
      This patch is providing possibility to use user defined reset-assert
      handler which will be enabled only in case SRST is disabled. It is
      needed to be able switch between two different reset variants on run
      Change-Id: I6ef98f1871ea657115877190f7cc7a5e8f3233e4
      Signed-off-by: default avatarOleksij Rempel <linux@rempel-privat.de>
      Reviewed-on: http://openocd.zylin.com/4404
      Tested-by: jenkins
      Reviewed-by: default avatarPaul Fertser <fercerpav@gmail.com>
  3. 22 Jun, 2018 1 commit
  4. 08 May, 2017 4 commits
  5. 10 Feb, 2017 1 commit
    • Dongxue Zhang's avatar
      target: Add 64-bit target address support · 47b8cf84
      Dongxue Zhang authored
      Define a target_addr_t type to support 32-bit and 64-bit addresses at
      the same time. Also define matching TARGET_PRI*ADDR format macros as
      well as a convenient TARGET_ADDR_FMT.
      In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000)
      be least invasive by leaving the formatting unchanged apart from the
      for generic code adopt TARGET_ADDR_FMT as unified address format.
      Don't silently change gdb formatting here, leave that to later.
      Add COMMAND_PARSE_ADDRESS() macro to abstract the address type.
      Implement it using its own parse_target_addr() function, in the hopes
      of catching pointer type mismatches better.
      Add '--disable-target64' configure option to revert to previous 32-bit
      target address behavior.
      Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5
      Signed-off-by: default avatarDongxue Zhang <elta.era@gmail.com>
      Signed-off-by: default avatarDavid Ung <david.ung.42@gmail.com>
      [AF: Default to enabling (Paul Fertser), rename macros, simplify]
      Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      Signed-off-by: default avatarMatthias Welwarsky <matthias.welwarsky@sysgo.com>
  6. 04 Oct, 2016 1 commit
  7. 24 May, 2016 1 commit
  8. 05 May, 2016 2 commits
    • Salvador Arroyo's avatar
      MIPS32 Fix typos · 7660c15f
      Salvador Arroyo authored
      I suppose 0xff300008 is the correct value for EJTAG_V20_DBS.
      20 miliseconds is too much for scan delay, 2ms is enough in mips_m4k scan_delay handler.
      mips32 scan_delay has the correct value.
      Change-Id: Ie9dc650065a58e845687058a4c930f85909beec9
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/2271
      Tested-by: jenkins
      Reviewed-by: default avatarKent Brinkley <jkbrinkley.imgtec@gmail.com>
      Reviewed-by: default avatarOleksij Rempel <linux@rempel-privat.de>
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
    • Tomas Vanek's avatar
      target: improve robustness of reset command · 88258042
      Tomas Vanek authored
      Before this change jim_target_reset() checked examined state of a target
      and failed without calling .assert_reset in particular target layer
      (and without comprehensible warning to user).
      Cortex-M target (which refuses access to DP under active SRST):
      If connection is lost then reset process fails before asserting SRST
      and connection with MCU is not restored.
      This resulted in:
      1) A lot of Cortex-M MCUs required use of reset button or cycling power
      after firmware blocked SWD access somehow (sleep, misconfigured clock etc).
      If firmware blocks SWD access early during initialization, a MCU could
      become completely inaccessible by SWD.
      2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive
      to SWD, reset command does not work even if it could help to restore communication.
      Hopefully this scenario is not possible under full JTAG.
      jim_target_reset() in target.c now does not check examined state
      and delegates this task to a particular target. All targets have been checked
      and xx_assert_reset() (or xx_deassert_reset()) procedures were changed
      to check examined state if needed. Targets except arm11, cortex_a and cortex_m
      just fail if target is not examined although it may be possible to use
      at least hw reset. Left as TODO for developers familiar with these targets.
      cortex_m_assert_reset(): memory access errors are stored
      instead of immediate returning them to a higher level.
      Errors from less important reads/writes are ignored.
      Requested reset always leads to a configured action.
      arm11_assert_reset() just asserts hw reset in case of not examined target.
      cortex_a_assert_reset() works as usual in case of not examined target.
      Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929
      Signed-off-by: default avatarTomas Vanek <vanekt@fbl.cz>
      Reviewed-on: http://openocd.zylin.com/2606
      Tested-by: jenkins
      Reviewed-by: default avatarMatthias Welwarsky <matthias@welwarsky.de>
      Reviewed-by: default avatarPaul Fertser <fercerpav@gmail.com>
  9. 19 Aug, 2014 2 commits
  10. 10 Jul, 2014 1 commit
  11. 31 Oct, 2013 2 commits
  12. 08 Sep, 2013 2 commits
  13. 17 Jul, 2013 1 commit
  14. 12 Jun, 2013 1 commit
    • Andreas Fritiofson's avatar
      [RFC] mips: Enable bulk write optimization for all writes · b8c44b3f
      Andreas Fritiofson authored
      mips_m4k_bulk_write_memory was only called from target_write_buffer as an
      optimization when the word count was large enough.
      Remove mips_m4k_bulk_write_memory from the target type, causing the default
      implementation to call the regular mips_m4k_write_memory instead.
      Perform the dispatch to bulk write in mips_m4k_write_memory, enabling the
      optimization for target_write_memory() writes with size 4, in addition to
      target_write_buffer() writes.
      It also enables making the choice of bulk write vs regular write
      specifically for the architecture and not relying on the generic target
      code to make a sensible decision.
      Change-Id: I295f21a67ceaa195802403f2518ea2e0a025c1c7
      Signed-off-by: default avatarAndreas Fritiofson <andreas.fritiofson@gmail.com>
      Reviewed-on: http://openocd.zylin.com/1215
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
      Tested-by: jenkins
  15. 05 Jun, 2013 1 commit
  16. 20 Apr, 2013 2 commits
    • Salvador Arroyo's avatar
      mips: m4k alternate pracc code. Patch 3 · d5e56462
      Salvador Arroyo authored
      Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
      mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
      mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
      Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
      To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
      mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
      restore it from ejtag info instead of using DeSave for save/restore.
      Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1195
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
    • Salvador Arroyo's avatar
      mips: m4k alternate pracc code. Patch 1 · 109f37c1
      Salvador Arroyo authored
      This patch and the following patches define another way of doing processor access without the need to read back
      the pracc address as needed in current pracc code.
      Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
      and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
      Most of the processor accesses are fetch and some are store accesses.
      After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
      The pracc address for a store depends only on the store instruction given before.
      m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
      will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
      For reference: MD00249 mips32 m4k manual.
      A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
      lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
      current code or by the new one to generate the sequence of pracc accesses.
      For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
      This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
      The pracc bit is not checked before execution, is checked after the queue has been executed.
      Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
      with core clock at 4Mhz works  up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
      between scans is added by calling jtag_add_cloks().
      A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
      A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
      current code is executed, if lower, new code is executed.
      Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
      Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1193
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
  17. 02 Apr, 2013 2 commits
    • Salvador Arroyo's avatar
      mips: code cleanup in cp0 command handlers · 74db7f96
      Salvador Arroyo authored
      After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary.
      Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1190
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
    • Salvador Arroyo's avatar
      mips: change in restoring debug working register · 37a6e402
      Salvador Arroyo authored
      In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack:
      And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack.
      Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug
      mode and can be modified by mips32_pracc_write_regs() when leaving debug mode.
      There is no need to read their values from the processor registers every time.
      The fields reg8 and reg9 are added to struct mips_ejtag to store these register values
      and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order
      to store them before any other function needs to restore these registers.
      For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed,
      should be made after calling mips_m4k_debug_entry().
      For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code,
      single word read takes now 10 instead of 12.
      This patch is really the first in a set of patches for an alternate m4k pracc code
      much faster that current code. At least for me with pic32mx works fine.
      Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1146
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
  18. 11 Dec, 2012 1 commit
  19. 09 Dec, 2012 1 commit
  20. 16 Nov, 2012 1 commit
    • Salvador Arroyo's avatar
      mips: code clean up in mips_m4k_debug_entry() function · 9aad563d
      Salvador Arroyo authored
      The function mips_ejtag_read_debug() is defined in mips_ejtag.c
      and is called only by mips_m4k_debug_entry() for reading the
      CP0 debug register. The comment in this function is obviously wrong.
      There is a generic function to read CP0 registers with similar code.
      A call to mips32_cp0_read() should work in the same way.
      The purpose of reading the debug register is to test if the DSS
      bit is set and clear the SSt bit.
      It is faster and easier if the SSt bit is cleared without any check.
      Remark: DSS bit set only means that a debug single-step exception
      ocurred, but it is not possible to step over a sdbbp instruction,
      in this case DSS will not be set and the SSt bit not cleared by code.
      Resume command at another address will step, so really the behavior
      is not the same.
      Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/950
      Tested-by: jenkins
      Reviewed-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
  21. 14 May, 2012 1 commit
  22. 14 Mar, 2012 1 commit
  23. 13 Mar, 2012 1 commit
  24. 06 Feb, 2012 1 commit
  25. 18 Jan, 2012 1 commit
  26. 04 Jan, 2012 2 commits
  27. 12 Aug, 2011 2 commits
  28. 09 Aug, 2011 2 commits
    • Drasko DRASKOVIC's avatar
      mips32 : Fixed memory byte access · 827057f5
      Drasko DRASKOVIC authored
      Function mips_m4k_write_memory() does endianess byte swap,
      but this procedure break one byte access (temporary array
      overwrites content in buffer).
      As a fix, this endianess swap and buffer affecting
      is preformed only on hword and word accesses (not on byte access).
    • Drasko DRASKOVIC's avatar
      mips32: Added CP0 coprocessor R/W routines · 1be71634
      Drasko DRASKOVIC authored
      This patch adds MIPS32 CP0 coprocessor R/W routines,
      as well as adequate commands to use these routines via
      telnet interface.
      Now is becomes possible to affect CP0 internal registers
      and configure CPU directly from OpenOCD.