Skip to content
GitLab
Switch branch/tag
  1. 17 Jul, 2009 1 commit
  3. 16 Jul, 2009 2 commits
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 1af6b72f
      zwelch authored 
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:

Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c.  There should be no
change in functionality here.  (From Magnus.)

Minor style cleanup:  whitespace, line length, etc.  Update spec
references to use docs which are currently available.  (From Dave.)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      1af6b72f
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 16e17ab1
      zwelch authored 
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:

Some cleanup of the ARMv7-M support:

 - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
   update the Cortex-M3 doc refs (DDI 0337C is no longer available).

 - Those registers aren't actually general, and some are incorrect (per all
   public docs anyway).  Update comments and code accordingly.

     * What the Core Debug facility exposes is *implementation-specific*
       not architectural.  These values aren't fully portable.  They match
       Cortex-M3 ... so no current implementation will make trouble, but
       the next v7m implementation might.

     * Four of the registers are actually not exposed that way.  Before
       Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
       In that newest silicon, they are four bytes in one register, not
       four separate registers.

 - Update the CM3 code to report when that one register is available,
   and not try to access it when it isn't.  Also declare the register
   numbers that an eventual MRS/MSR solution will need to be using.

 - Stop line wrapping the exception labels.

So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.

Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts.  Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      16e17ab1
  5. 23 Jun, 2009 5 commits
  7. 21 Jun, 2009 1 commit
  9. 18 Jun, 2009 3 commits
  11. 02 Jun, 2009 1 commit
    • ntfreak's avatar
      - change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use... · 7dc29156
      ntfreak authored 
      - change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use swjdp_common_t *swjdp instead of arm_jtag_t *jtag_info
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs.
- add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus
- Set default memaccess value to 8 for Cortex-M3.
- Add dap memaccess command.
- document all armv7 dap cmds.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].

git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7dc29156
  13. 31 May, 2009 1 commit
  15. 11 May, 2009 1 commit
  17. 06 May, 2009 1 commit
  19. 27 Apr, 2009 2 commits
  21. 19 Apr, 2009 1 commit
  23. 03 Apr, 2009 1 commit
  25. 20 Nov, 2008 1 commit
  27. 06 Nov, 2008 1 commit
  29. 02 Nov, 2008 1 commit
  31. 14 Oct, 2008 2 commits
  33. 13 Oct, 2008 1 commit
  35. 07 Oct, 2008 2 commits
  37. 20 Sep, 2008 1 commit
  39. 24 Aug, 2008 1 commit
  41. 20 Aug, 2008 1 commit
  43. 27 May, 2008 1 commit
  45. 26 Apr, 2008 1 commit
  47. 11 Apr, 2008 1 commit
  49. 10 Apr, 2008 1 commit
    • ntfreak's avatar
      - single core context used, removed debug context as thought unnecessary. · 9c3dec37
      ntfreak authored 
      - DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit

git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      9c3dec37
  51. 25 Mar, 2008 1 commit
  53. 22 Mar, 2008 1 commit
  55. 21 Mar, 2008 1 commit
  57. 11 Mar, 2008 1 commit
  59. 10 Mar, 2008 1 commit
    • oharboe's avatar
      - the jtag chain is examined and validated after GDB & telnet servers · e6dac739
      oharboe authored 
       are up and running. The examination and validation is actually
 "optional" from the point of view of GDB + telnet servers.
 Multiple targets should work fine with this.
- jtag_speed is dropped(divisor is increased), if jtag examination and
 validation fails.
- the chain is validated 10x to catch the worst jtag_speed offences
- added LOG_SILENT that can be used to shut up log. Feeble
 ersatz for try+catch.
- GDB register packets are now always replied in order to make sure
 that GDB connect works. If the target is not halted, then these
 packets contain dummy values.



git-svn-id: svn://svn.berlios.de/openocd/trunk@483 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      e6dac739