1. 17 Jul, 2009 1 commit
  2. 16 Jul, 2009 4 commits
    • oharboe's avatar
      microscopic whitespace cleanup · bd437719
      oharboe authored
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2547 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • oharboe's avatar
      microscopic white space fixes · 4deb8530
      oharboe authored
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2546 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 1af6b72f
      zwelch authored
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
      Move the dap command handler implementations to arm_adi_v5.c,
      leaving just thin wrappers in armv7m.c.  There should be no
      change in functionality here.  (From Magnus.)
      Minor style cleanup:  whitespace, line length, etc.  Update spec
      references to use docs which are currently available.  (From Dave.)
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 16e17ab1
      zwelch authored
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
      Some cleanup of the ARMv7-M support:
       - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
         update the Cortex-M3 doc refs (DDI 0337C is no longer available).
       - Those registers aren't actually general, and some are incorrect (per all
         public docs anyway).  Update comments and code accordingly.
           * What the Core Debug facility exposes is *implementation-specific*
             not architectural.  These values aren't fully portable.  They match
             Cortex-M3 ... so no current implementation will make trouble, but
             the next v7m implementation might.
           * Four of the registers are actually not exposed that way.  Before
             Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
             In that newest silicon, they are four bytes in one register, not
             four separate registers.
       - Update the CM3 code to report when that one register is available,
         and not try to access it when it isn't.  Also declare the register
         numbers that an eventual MRS/MSR solution will need to be using.
       - Stop line wrapping the exception labels.
      So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
      still buggy; but for those newer parts a few things might now be correct.
      Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
      most LM3S parts and all STM32 parts.  Parts using r2p0 are available, and
      include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
      parts which are now sampling.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
  3. 15 Jul, 2009 14 commits
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 0c2ff267
      zwelch authored
      More 32-bit Thumb2 instruction decoding:
      	A5.3.7 Load word 
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · fdfd434c
      zwelch authored
      More 32-bit Thumb2 instruction decoding:
      	A5.3.12 Data processing (register)
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2541 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 00adcc77
      zwelch authored
      More 32-bit instruction decoding:
      	A5.3.11 Data processing (shifted register)
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2540 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 930269b4
      zwelch authored
      More instructions decoded:
      	A5.3.5 Load/store multiple 
      The preferred PUSH/POP syntax is shown when appropriate.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 421b8e13
      zwelch authored
      More instructions decoded:
      	A5.3.14 Multiply, and multiply accumulate 
      	A5.3.15 Long multiply, long multiply accumulate, divide
      The EABI requires *adjacent* register pairs, but the long multiply
      ops can use any pair of registers; interesting.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 889bd3e7
      zwelch authored
      More Thumb2 32-bit opcode support:
      	 A5.3.10 Store single data item 
      Byte, word, halfword.  Offset, pre-index, post-index.  And
      a "make like you're unprivileged" option when using small
      immediate offsets.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 84e86e9a
      zwelch authored
      Print old-style Thumb NOP instructions as such.  (GCC uses "mov r8, r8"
      instead of the architected NOP which is new in Thumb2.)
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · d2088f0d
      zwelch authored
      Make disassembly of the Thumb load-literal instruction show the
      address of the literal being loaded (so users can avoid doing
      that math themselves).  Add and use an Align(PC,4) utility.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · f163d000
      zwelch authored
      Make the Thumb2 disassembler handle more 32-bit instructions:
        A5.3.3 Data processing (plain binary immediate)
      These use mostly twelve bit literals, but there are also bitfield
      and saturated add primitives.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 0165ae44
      zwelch authored
      Make the Thumb2 disassembler handle more 32-bit instructions:
        A5.3.1 Data processing (modified immediate)
      My small sample shows GCC likes to use many of these instructions.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 8b89224c
      zwelch authored
      Make the Thumb2 disassembler handle a bunch of 32-bit instructions:
        A5.3.4 Branches and miscellaneous control
      Note that this shifts some responsabililty out of helper functions,
      making the code and layout simpler for 32-bit decoders:  they only
      need to know how to format the instruction and its parameters.
      Also, technical note:  with this patch, Thumb1 decoders could now
      call the Thumb2 decoder if they wanted to get nicer treatment of
      the exiting 32-bit B/BLX instructions.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · b71e3aff
      zwelch authored
      Change layout of Thumb disassembly to work better with Thumb2:
       - Move opcode to the left, allowing space for four hex bytes:
          * after address, two spaces not one tab (taking 6 spaces)
          * after 2-byte opcode, four spaces before tab
       - Also, after opcode mnemonic use a tab not a space, to make
         operands line up
      Sample output (after some patches decoding a few 32-bit instructions):
      0x00003e5a  0xf4423200	ORR	r2, r2, #131072	; 0x20000
      0x00003e5e  0x601a    	STR 	r2, [r3, #0x0]
      0x00003e60  0x2800    	CMP	r0, #0x00
      0x00003e62  0xd1f3    	BNE	0x00003e4c
      0x00003e64  0xf008fa38	BL	0x0000c2d8
      The affected lines of code now wrap at sane margins too.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 309870e4
      zwelch authored
      Initial support for disassembling Thumb2 code.  This works only for
      Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
      support ... but they don't yet support any kind of disassembly.
       - Update the 16-bit Thumb decoder:
           * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
             by ARMv6.  (It already seems to treat CPY as MOV.)
           * Understand CB, CBNZ, WFI, IT, and other opcodes added by
             in Thumb2.
       - A new Thumb2 instruction decode routine is provided.
           * This has a different signature:  pass the target, not the
             instruction, so it can fetch a second halfword when needed.  
             The instruction size is likewise returned to the caller.
           * 32-bit instructions are recognized but not yet decoded.
       - Start using the current "UAL" syntax in some cases.  "SWI" is
         renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".
       - Define a new "cortex_m3 disassemble addr count" command to give
         access to this disassembly.
      Sanity checked against "objdump -d" output; a bunch of the new
      instructions checked out fine.
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
    • oharboe's avatar
      print errno when parport fails to open. · 2ff59c9a
      oharboe authored
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2529 b42882b7-edfa-0310-969c-e2dbd0fdcd60
  4. 14 Jul, 2009 1 commit
  5. 13 Jul, 2009 1 commit
  6. 12 Jul, 2009 1 commit
  7. 11 Jul, 2009 1 commit
  8. 08 Jul, 2009 2 commits
  9. 07 Jul, 2009 2 commits
  10. 06 Jul, 2009 13 commits