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  1. 09 Nov, 2009 1 commit
    • David Brownell's avatar
      Revert "target: add target->type->has_mmu fn" · 7269ba5e
      David Brownell authored 
      

This patch introduced a bug preventing flash writes from working
on Cortex-M3 targets like the STM32.  Moreover, it's the wrong
approach for handling no-MMU targets.

The right way to handle no-MMU targets is to provide accessors
for physical addresses, and use them everywhere; and any code
which tries to work with virtual-to-physical mappings should use
a identity mapping (which can be defaulted).

And ... we can tell if a target has an MMU by seeing if it's
got an mmu() method.  No such methood means no MMU.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      7269ba5e
  3. 08 Nov, 2009 1 commit
  5. 06 Nov, 2009 2 commits
  7. 05 Nov, 2009 7 commits
    • David Brownell's avatar
      watchpoint_add() cleanup · 98788d7a
      David Brownell authored 
      

Fail watchpoint_add() if it's the same address but the
parameters are different ... don't just assume having
the same address means the same watchpoint!  (Note that
overlapping watchpoints aren't detected...)

Handle unrecognized return codes more sanely; don't exit()!
And describe command params right.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      98788d7a
    • David Brownell's avatar
      Cortex-M3: expose most DWT registers · 16b4b8cf
      David Brownell authored 
      

Expose most DWT registers via Tcl; there are a few more, but
those are mostly for profiling along with the ITM.  Having
this set available enables operations which aren't possible
with just the standard watchpoint operations.

The cycle counter may be interesting.  Turn it on after reset
by setting the LSB of the dwt_ctrl register, and it counts
CPU clocks.  You can program the comparator 0 watchpoint to
trigger on a given cycle count, rather than a data address.

Likewise, comparator 1 may be able to match data values given
address matches from one or two other comparators.  (Not all
hardware supports this capability though; try it.  That is
something the standard watchpoint methods should eventually
handle, for the single address case.)

Minor cleanup:  remove needless functional indirection for
exposing the v7m architctural registers.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      16b4b8cf
    • David Brownell's avatar
      Cortex-M3: minor cleanup · 8fb2baaa
      David Brownell authored 
      

There's no reason to read which interrupts are enabled from
the NVIC; that state isn't used.  Plus, it's highly dynamic
since firmware can change it at any time; remove the support
for those state records.

Remove duplicate definition of DWT_CTRL address; shrink a line.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      8fb2baaa
    • David Brownell's avatar
      Cortex-M3: DWT cleanup/fixes · 7acb2607
      David Brownell authored 
      

Fix the watchpoint error checks, and do them in add(), not later
in set() when it's mostly too late.  Support the full range of
watchpoint sizes (1 to 32K bytes each), and check alignments.

Minor cleanup of DWT access:  shrink lines, use "+" for address
calculations, comment a few issues.  Add debug message reporting
DWT capabilities, matching the message for FBP, and some minor
code and spec review comments.
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      7acb2607
    • Øyvind Harboe's avatar
      target: add target->type->has_mmu fn. · d269122f
      Øyvind Harboe authored 
      

improve default target->read/write_phys_memory, produce
more sensible error messages if the mmu interface
functions have not been implemented yet vs. will
not be implemented(e.g. cortex m3).
Signed-off-by: default avatarØyvind Harboe <oyvind.harboe@zylin.com>
      d269122f
    • Øyvind Harboe's avatar
      target: remove unused interface fn that clutters code · af66678c
      Øyvind Harboe authored 
      

The quit entry point was not being invoked. Just a source
of confusion at this point. XScale ran 100x reset upon
quit, but that code made no sense, wasn't commented
and never invoke.
Signed-off-by: default avatarØyvind Harboe <oyvind.harboe@zylin.com>
      af66678c
    • Øyvind Harboe's avatar
      debug interface: get rid of unused pre_debug fn · acff2521
      Øyvind Harboe authored 
      

Removing unused code makes it much less mysterius.
Signed-off-by: default avatarØyvind Harboe <oyvind.harboe@zylin.com>
      acff2521
  9. 28 Oct, 2009 1 commit
  11. 01 Sep, 2009 1 commit
  13. 25 Aug, 2009 1 commit
    • oharboe's avatar
      David Brownell <david-b@pacbell.net> Tweak disassembly commands: · bc075606
      oharboe authored 
       For ARMv4/ARMv5:
  - better command parameter error checking
  - don't require an instruction count; default to one
  - recognize thumb function addresses
  - make function static
  - shorten some too-long lines
 For Cortex-M3:
  - don't require an instruction count; default to one

With the relevant doc updates.
---
Nyet done:  invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      bc075606
  15. 19 Aug, 2009 1 commit
    • oharboe's avatar
      David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling. · 57578b4e
      oharboe authored 
       - AIRCR_SYSRESETREQ is generic; use it on any system where
  SRST won't fly, not just on Stellaris-based ones.

 - Reformat and improve comments about the Stellaris quirk; and
  xref the only public docs (an email) about the issue.

It seems that *most* Stellaris chips have this problem.  Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      57578b4e
  17. 18 Aug, 2009 1 commit
  19. 21 Jul, 2009 2 commits
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · 4da019ed
      ntfreak authored 
      Clean up treatment of registers in ARMv7-M and Cortex-M3. 

 - At the arch level:
    * Just list registers and names; don't impose core-specific
      policy about how they are accessed.
    * Each register has a symbol.
    * Remove the register mode field (irrelevant to debugger)

 - At the core/implementation level:
    * Just map the registers to their relevant access methods;
      don't require the arch level to say how that should work
      (cores other than Cortex-M3 could do it differently).
    * Don't use undefined bits from register 20.
    * Use register IDs that are part of the ARMv7-M interface.

In short, there's now a real distinction between the arch
and core layers.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      4da019ed
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · cd0ca916
      ntfreak authored 
      Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      cd0ca916
  21. 16 Jul, 2009 1 commit
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 16e17ab1
      zwelch authored 
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:

Some cleanup of the ARMv7-M support:

 - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
   update the Cortex-M3 doc refs (DDI 0337C is no longer available).

 - Those registers aren't actually general, and some are incorrect (per all
   public docs anyway).  Update comments and code accordingly.

     * What the Core Debug facility exposes is *implementation-specific*
       not architectural.  These values aren't fully portable.  They match
       Cortex-M3 ... so no current implementation will make trouble, but
       the next v7m implementation might.

     * Four of the registers are actually not exposed that way.  Before
       Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
       In that newest silicon, they are four bytes in one register, not
       four separate registers.

 - Update the CM3 code to report when that one register is available,
   and not try to access it when it isn't.  Also declare the register
   numbers that an eventual MRS/MSR solution will need to be using.

 - Stop line wrapping the exception labels.

So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.

Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts.  Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      16e17ab1
  23. 15 Jul, 2009 1 commit
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 309870e4
      zwelch authored 
      Initial support for disassembling Thumb2 code.  This works only for
Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.

 - Update the 16-bit Thumb decoder:
 
     * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
       by ARMv6.  (It already seems to treat CPY as MOV.)

     * Understand CB, CBNZ, WFI, IT, and other opcodes added by
       in Thumb2.

 - A new Thumb2 instruction decode routine is provided.
 
     * This has a different signature:  pass the target, not the
       instruction, so it can fetch a second halfword when needed.  
       The instruction size is likewise returned to the caller.

     * 32-bit instructions are recognized but not yet decoded.
   
 - Start using the current "UAL" syntax in some cases.  "SWI" is
   renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".

 - Define a new "cortex_m3 disassemble addr count" command to give
   access to this disassembly.

Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      309870e4
  25. 12 Jul, 2009 1 commit
  27. 28 Jun, 2009 1 commit
  29. 27 Jun, 2009 1 commit
  31. 23 Jun, 2009 8 commits
  33. 21 Jun, 2009 1 commit
  35. 18 Jun, 2009 3 commits
  37. 09 Jun, 2009 2 commits
  39. 04 Jun, 2009 1 commit
  41. 02 Jun, 2009 1 commit
    • ntfreak's avatar
      - change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use... · 7dc29156
      ntfreak authored 
      - change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use swjdp_common_t *swjdp instead of arm_jtag_t *jtag_info
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs.
- add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus
- Set default memaccess value to 8 for Cortex-M3.
- Add dap memaccess command.
- document all armv7 dap cmds.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].

git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7dc29156
  43. 01 Jun, 2009 1 commit