1. 25 Nov, 2009 3 commits
  2. 24 Nov, 2009 5 commits
    • David Brownell's avatar
      ARM11: remove old R0..R15/CPSR code · 3efc99b3
      David Brownell authored
      
      
      This finishes the basic switchover to the new register code,
      for everything except the debug registers.  (And maybe we
      shouldn't have a cache for *those* which works this way...)
      
      The context save/restore code now uses the new code, but
      it's in a slightly different sequence.  That should be fine
      since the R0/PC/CPSR stuff is all that really matters (and
      if we can update those, we can update the rest).
      
      Now there's no longer a way any code can be confused about
      which copy of "r1" (etc) to use.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      3efc99b3
    • David Brownell's avatar
      ARM11: use standard run_algorithm() · ec64acf5
      David Brownell authored
      
      
      As with single stepping, the previous stuff was needed because
      the ARM11 code wasn't using the standard ARM base type and
      register access ... but now those mechanisms work, so we can
      switch out that special-purpose glue, in favor of the more
      thoroughly tested/capable "standard" code.
      
      Fixes a bug in the resume() implementation:  it wasn't handling
      two of its arguments correctly, preventing the "flash erase_check"
      algorithm from working.  (This code needs a *subsequent* update
      for correct register handling, though... removing the confusion
      about which "r2", for example, to use.)
      
      This should resolve some "FIXME" comments too, for Thumb and
      processor mode support.  It also gets rid of a nasty exit()
      call; servers should only have *clean* shutdown paths.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      ec64acf5
    • David Brownell's avatar
      ARM11: use standard single step simulation · bf3abc48
      David Brownell authored
      
      
      The previous stuff was needed because the ARM11 code wasn't using
      the standard ARM base type and register access ... but now those
      mechanisms work, so we can switch out that special-purpose glue.
      
      This should resolve all the "FIXME -- handle Thumb single stepping"
      comments too, and properly handle the processor's mode.  (Modulo
      the issue that this code doesn't yet handle two-byte breakpoints.)
      
      Clarify the comments about the the hardware single stepping.  When
      we eventually share breakpoint code with Cortex-A8, we can just make
      that be the default on cores which support it.  We may still want an
      override command, not just to facilitate testing but to cope with
      "instruction address mismatch" not quite being true single-step.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      bf3abc48
    • David Brownell's avatar
      ARM11: partial support for standard ARM register interfaces. · 5eb893ec
      David Brownell authored
      
      
      This provides "standard" ARM register support -- with twenty or
      more shadow registers on top of what this code now handles, but
      properly associated with the various core modes -- parallel to
      the current register code.  That is, the current code is stilil
      managing the "current" registers; the new code shadows them.
      
      You can see all the registers with "arm reg", modify the shadows
      like "r8_fiq" or "sp_abt" with "reg", and see them get properly
      written back when you step.  (Just don't do that with any of the
      registers managed by the "old" code ...)
      
      It also switches to using more standard code, relying on those
      standard registers, in two places:  (a) the poll status display,
      which now shows core state (ARM/Thumb/...) and mode (Supervisor,
      IRQ, etc); and (b) GDB register access.
      
      So it's not a full migration, there are warts -- every place that
      touches the old register cache is a potential bug -- but it's a
      small more-or-less-comprehensible step that's even somewhat useful.
      Later patches complete the migration.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      5eb893ec
    • David Brownell's avatar
      ARM11: remove register "history" debug stuff · 6ff33a4e
      David Brownell authored
      
      
      This was a private mechanism to snapshot registers before leaving
      debug state, and then on reentry to optionally display what changed.
      It was coupled to the private register cache, which won't be sticking
      around in that form for much longer.  Remove (instead of teaching
      it how to handle *all* the registers).
      
      (The idea is interesting, but we ought to be able to implement
      this in a generic way.  Ideally through Tcl scripts that can
      automatically be invoked following debug entry...)
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      6ff33a4e
  3. 22 Nov, 2009 4 commits
  4. 18 Nov, 2009 4 commits
    • Zachary T Welch's avatar
      add handle_command_parse_bool command helper · 7e4adfe1
      Zachary T Welch authored
      Rewrite arm11_handle_bool to provide a generic on/off command helper.
      
      Refactors COMMAND_PARSE_BOOL to use new command_parse_bool helper,
      which gets reused by the new command_parse_bool_any helper.
      This later helper is called by the new command helper function to
      accepts any on/off, enable/disable, true/false, yes/no, or 0/1 parameter.
      7e4adfe1
    • David Brownell's avatar
      ARM: add "core_type" field to "struct arm" · bbebfd9e
      David Brownell authored
      
      
      It's used to flag cores with the "TrustZone" extension,
      and is used in subsequent patches to set up support for
      the registers shadowed by its new secure monitor mode.
      
      The ARM1176 and Cortex-A8 both support this new mode.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      bbebfd9e
    • David Brownell's avatar
      ARM: add is_arm_mode() · 181d401d
      David Brownell authored
      
      
      Add a new is_arm_mode() predicate, and use it to replace almost
      all calls to current armv4_5_mode_to_number().
      
      Eventually those internal mode numbers should vanish... along
      with their siblings in the armv7a.c file.
      
      Remove a handful of superfluous checks ... e.g. the mode number
      was just initialized, or (debug entry methods) already validated.
      
      Move one of the macros using internal mode numbers into the only
      file which uses that macro.  Make the tables manipulated with
      those numbers be read-only and, where possible, static so they're
      not confused with part of the generic ARM interface.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      181d401d
    • David Brownell's avatar
      ARM: only use one set of dummy FPA registers · d6c89456
      David Brownell authored
      
      
      All ARM cores need to provide obsolete FPA registers in their
      GDB register dumps.  (Even though cores with floating point
      support now generally use some version of VFP...)
      
      Clean up that support a bit by sharing the same dummy registers,
      and removing the duplicate copies.  Eventually we shouldn't need
      to export those dummies.
      
      (This makes the ARMv7-M support include the armv4_5 header, and
      cleans up related #includes, but doesn't yet use anything from
      there except those dummies.)
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      d6c89456
  5. 17 Nov, 2009 6 commits
  6. 16 Nov, 2009 5 commits
  7. 15 Nov, 2009 3 commits
    • David Brownell's avatar
      ARM11: use now-generic memory utils · 5d1a9033
      David Brownell authored
      
      
      Now the ARM11 cores can use the renamed arm_checksum_memory()
      and arm_blank_check_memory() routines ... do so.
      
      Sanity checked with "flash erase_check" of both NOR banks on an
      OMAP2420 ... the algorithm code dumped four lines of of "poll"
      status after each of almost 520 blocks (yes, *very* annoying) but
      gave plausible results after producing that spam.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      5d1a9033
    • David Brownell's avatar
      ARM11: fixup method table · 2280ddee
      David Brownell authored
      
      
      Three changes:  remove ARM11_HANDLER() in favor of normal structure
      initialization syntax; fix goofy indentation in that structure; and
      don't needlessly export arm11_register_commands(), it's only called
      through that method table.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      2280ddee
    • David Brownell's avatar
      target: make "examined" flag be per-target · 9ac7cdec
      David Brownell authored
      
      
      Previously this flag was stored in "target_type", so that for example
      if there were two ARM7TDMI targets in a scan chain, both would claim
      to have been examined although only the first one actually had its
      examine() method called.
      
      Move this state to where it should have been in the first place, and
      hide a method that didn't need exposure ... the flag is write-once.
      
      Provide some doxygen.  The examine() method is confusing, since it
      isn't separating one-time setup from the after-each-reset stuff.  And
      the ARM7/ARM9 version is, somewhat undesirably, not leaving the debug
      state alone after reset ... probably more of an issue for trace setup
      than for watchpoints and breakpoints.
      
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      9ac7cdec
  8. 14 Nov, 2009 4 commits
  9. 13 Nov, 2009 6 commits