- 04 Jan, 2012 1 commit
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Øyvind Harboe authored
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by:
Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by:
Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by:
Spencer Oliver <spen@spen-soft.co.uk>
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- 07 Nov, 2011 1 commit
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Øyvind Harboe authored
return error message instead. Found by clang. Change-Id: Ica109d077206236a12d007e77cc78061ffd05834 Signed-off-by:
Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/169 Tested-by: jenkins Reviewed-by:
Spencer Oliver <spen@spen-soft.co.uk>
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- 04 Jun, 2011 1 commit
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Freddie Chopin authored
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- 29 Dec, 2010 1 commit
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Øyvind Harboe authored
Signed-off-by:
Øyvind Harboe <oyvind.harboe@zylin.com>
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- 22 Jan, 2010 1 commit
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David Brownell authored
Doxygen: don't be needlessly verbose; alphabetically sort members TODO: add random bits; clarify which manuals are referenced ARM disassembler: mention a few opcodes that still aren't handled Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 12 Jan, 2010 1 commit
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David Brownell authored
Use the correct bitfield to specify the register whose top halfword gets replaced. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 15 Dec, 2009 1 commit
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David Brownell authored
There is no "STMMIDA" instruction. There is however "STMDAMI". Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 11 Dec, 2009 1 commit
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David Brownell authored
Properly detect all of these, including the "2" variants; and bugfix parameter display for LDC and STC. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 08 Dec, 2009 2 commits
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David Brownell authored
It's as if despite integers being 32-bits, GCC refuses to convert a "uint32_t" to one of them. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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David Brownell authored
Some versions of GCC don't understand that if you mask with 0x3 then have cases 0-3, it's not possible for a variable assigned in all those branches to have no value at end-of-case. Feh. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 07 Dec, 2009 1 commit
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David Brownell authored
The SRS and RFE instructions speed exception entry/exit by making it easy to save and restore PC and SPSR. This handles both ARM and Thumb2 encodings. Fix minor PLD goofage; that "should never reach this point" can't happen, so remove it. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 03 Dec, 2009 1 commit
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Zachary T Welch authored
Changes from the flat namespace to heirarchical one. Instead of writing: #include "log.h" the following form should be used. #include <helper/log.h> The exception is from .c files in the same directory.
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- 16 Nov, 2009 1 commit
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David Brownell authored
Tweak "standard" ARM disassembler diagnostics to fail if the target is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for cores inheriting this as the "generic" disassembler. Also, to use the Thumb2 entry instead of the original Thumb entry. This makes it work better for both newer cores (which support those added instructions) and for BL and BLX instructions on older cores. (Those instructions are 32-bits, which requires curious state-aware code to go through a 16-bit decode interface...) Plus minor cleanups, notably to have fewer exit paths and to make sure they all return failure codes. Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 13 Nov, 2009 2 commits
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Zachary T Welch authored
Remove misleading typedef and redundant suffix from struct target.
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Zachary T Welch authored
Remove misleading typedef and redundant suffix from struct arm_instruction.
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- 28 Oct, 2009 1 commit
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Nicolas Pitre authored
A Thumb BLX instruction is branching to ARM code, and therefore the first 2 bits of the target address must be cleared. Signed-off-by:
Nicolas Pitre <nico@marvell.com> Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 13 Oct, 2009 1 commit
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Lennert Buytenhek authored
Signed-off-by:
Lennert Buytenhek <buytenh@marvell.com> Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net>
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- 08 Sep, 2009 1 commit
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oharboe authored
lean up some loose ends with the ARM disassembler - Add a header comment describing its current state and uses and referencing the now-generally-available V7 arch spec - Support some mode switch instructions: * Thumb to Jazelle (BXJ) * Thumb to ThumbEE (ENTERX) * ThumbEE to Thumb (LEAVEX) - Improve that recent warning fix (and associated whitespace goof) - Declare the rest of the internal code and data "static". A compiler may use this, and it helps clarify the scope of these routines (e.g. what changes to them could affect). git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 31 Aug, 2009 1 commit
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duane authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 28 Aug, 2009 1 commit
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oharboe authored
David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions that were added after ARMv5TE was defined: - ARMv5J "BXJ" (for Java/Jazelle) - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc) Compile-tested. This might not set up the simulator right for the ARMv6 single step support; only BXJ branches though, and docs to support Jazelle branching are non-public (still, sigh). ARMv6 instructions known to be mis-handled by this disassembler include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2 git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 20 Aug, 2009 1 commit
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oharboe authored
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch GCC will generate the table branch instructions, usually with inlined tables that will confuse this disassembler. LDREX and STREX are not issued by GCC without inline assembly. This means all Thumb2 instructions implemented by Cortex-M3 can now be disassembled. Cortex-A8 cores support more Thumb2 instructions, but most of those aren't yet publicly documented. git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 16 Aug, 2009 1 commit
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 26 Jul, 2009 4 commits
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oharboe authored
A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 24 Jul, 2009 3 commits
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oharboe authored
ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 23 Jul, 2009 3 commits
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 21 Jul, 2009 1 commit
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ntfreak authored
Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- 15 Jul, 2009 7 commits
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zwelch authored
More 32-bit Thumb2 instruction decoding: A5.3.7 Load word git-svn-id: svn://svn.berlios.de/openocd/trunk@2542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
More 32-bit Thumb2 instruction decoding: A5.3.12 Data processing (register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2541 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
More 32-bit instruction decoding: A5.3.11 Data processing (shifted register) git-svn-id: svn://svn.berlios.de/openocd/trunk@2540 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
More instructions decoded: A5.3.5 Load/store multiple The preferred PUSH/POP syntax is shown when appropriate. git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
More instructions decoded: A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, divide The EABI requires *adjacent* register pairs, but the long multiply ops can use any pair of registers; interesting. git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
More Thumb2 32-bit opcode support: A5.3.10 Store single data item Byte, word, halfword. Offset, pre-index, post-index. And a "make like you're unprivileged" option when using small immediate offsets. git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8" instead of the architected NOP which is new in Thumb2.) git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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