1. 04 Jan, 2012 1 commit
  2. 07 Nov, 2011 1 commit
  3. 04 Jun, 2011 1 commit
  4. 29 Dec, 2010 1 commit
  5. 22 Jan, 2010 1 commit
  6. 12 Jan, 2010 1 commit
  7. 15 Dec, 2009 1 commit
  8. 11 Dec, 2009 1 commit
  9. 08 Dec, 2009 2 commits
  10. 07 Dec, 2009 1 commit
  11. 03 Dec, 2009 1 commit
    • Zachary T Welch's avatar
      change #include "log.h" to <helper/log.h> · c79cca04
      Zachary T Welch authored
      Changes from the flat namespace to heirarchical one.  Instead of writing:
      
      	#include "log.h"
      
      the following form should be used.
      
      	#include <helper/log.h>
      
      The exception is from .c files in the same directory.
      c79cca04
  12. 16 Nov, 2009 1 commit
    • David Brownell's avatar
      ARM: standard disassembler uses Thumb2 entry · 91ac164d
      David Brownell authored
      
      
      Tweak "standard" ARM disassembler diagnostics to fail if the target
      is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for
      cores inheriting this as the "generic" disassembler.
      
      Also, to use the Thumb2 entry instead of the original Thumb entry.
      This makes it work better for both newer cores (which support those
      added instructions) and for BL and BLX instructions on older cores.
      (Those instructions are 32-bits, which requires curious state-aware
      code to go through a 16-bit decode interface...)
      
      Plus minor cleanups, notably to have fewer exit paths and to make
      sure they all return failure codes.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      91ac164d
  13. 13 Nov, 2009 2 commits
  14. 28 Oct, 2009 1 commit
  15. 13 Oct, 2009 1 commit
  16. 08 Sep, 2009 1 commit
    • oharboe's avatar
      David Brownell <david-b@pacbell.net> · 57e12b7e
      oharboe authored
      lean up some loose ends with the ARM disassembler
      
       - Add a header comment describing its current state and uses
         and referencing the now-generally-available V7 arch spec
      
       - Support some mode switch instructions:
          * Thumb to Jazelle (BXJ)
          * Thumb to ThumbEE (ENTERX)
          * ThumbEE to Thumb (LEAVEX)
      
       - Improve that recent warning fix (and associated whitespace goof)
      
       - Declare the rest of the internal code and data "static".  A
         compiler may use this, and it helps clarify the scope of these
         routines (e.g. what changes to them could affect).
      
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      57e12b7e
  17. 31 Aug, 2009 1 commit
  18. 28 Aug, 2009 1 commit
    • oharboe's avatar
      David Brownell <david-b@pacbell.net> ARM disassembly support for about five... · 997d5284
      oharboe authored
      David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
      that were added after ARMv5TE was defined:
      
       - ARMv5J "BXJ" (for Java/Jazelle)
       - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)
      
      Compile-tested.  This might not set up the simulator right for the
      ARMv6 single step support; only BXJ branches though, and docs to
      support Jazelle branching are non-public (still, sigh).
      
      ARMv6 instructions known to be mis-handled by this disassembler
      include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      997d5284
  19. 20 Aug, 2009 1 commit
    • oharboe's avatar
      David Brownell <david-b@pacbell.net>More Thumb2 disassembly: · 028e5356
      oharboe authored
        ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
      
      GCC will generate the table branch instructions, usually with inlined
      tables that will confuse this disassembler.  LDREX and STREX are not
      issued by GCC without inline assembly.
      
      This means all Thumb2 instructions implemented by Cortex-M3 can now
      be disassembled.  Cortex-A8 cores support more Thumb2 instructions,
      but most of those aren't yet publicly documented.
      
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      028e5356
  20. 16 Aug, 2009 1 commit
  21. 26 Jul, 2009 4 commits
  22. 24 Jul, 2009 3 commits
  23. 23 Jul, 2009 3 commits
  24. 21 Jul, 2009 1 commit
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · eea04862
      ntfreak authored
      Minor updates to the Thumb2 disassembly:
      
       - Bugfixes:
          * Distinguish branch from misc via "!=" not "=="
          * MRS register shift is 8 bits (vs MSR being 16)
       - Format tweaks:
          * CPS needed tab (not space)
          * add commma before some shifts
          * add space after comma in LDM/STM
          * use ".W" width spec on various instructions
      
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      eea04862
  25. 15 Jul, 2009 7 commits