1. 03 Mar, 2010 2 commits
    • David Brownell's avatar
      ADIv5: use new DAP ops for AP read/write · 381ce430
      David Brownell authored
      Make ADIv5 internals use the two new transport-neutral calls for reading
      and writing DP registers; and do the same for external callers.  Also,
      bugfix some of their call sites to handle the fault returns, instead of
      ignoring them.
      Remove most of the JTAG-specific calls, using their code as the bodies
      of the JTAG-specific implementation for the new methods.
      NOTE that there's a remaining issue:  mem_ap_read_buf_u32() makes calls
      which are JTAG-specific.  A later patch will need to remove those, so
      JTAG-specific operations can be removed from this file, and so that SWD
      support will be able to properly drop in as just a transport layer to the
      ADIv5 infrastructure.  (The way read results are posted may need some more
      attention in the transport-neutrality interface.)
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      ADIv5: use new dap_run() operation · 24b1426a
      David Brownell authored
      Make ADIv5 use one of the new transport-neutral interfaces: call
      dap_run(), not jtagdp_transaction_endcheck().
      Also, make that old interface private; and bugfix some of its call
      sites to handle the fault returns, instead of ignoring them.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  2. 28 Feb, 2010 2 commits
  3. 21 Feb, 2010 4 commits
    • David Brownell's avatar
      ADIv5: remove ATOMIC/COMPOSITE interface mode · 3b68a708
      David Brownell authored
      This removes context-sensitivity from the programming interface and makes
      it possible to know what a block of code does without needing to know the
      previous history (specifically, the DAP's "trans_mode" setting).
      The mode was only set to ATOMIC briefly after DAP initialization, making
      this patch be primarily cleanup; almost everything depends on COMPOSITE.
      The transactions which shouldn't have been queued were already properly
      flushing the queue.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      ADIv5 clean up AP selection and register caching · 249263d2
      David Brownell authored
      Handling of AP (and AP register bank) selection, and cached AP
      registers, is pretty loose ... start tightening it:
       - It's "AP bank" select support ... there are no DP banks.  Rename.
         + dap_dp_bankselect() becomes dap_ap_bankselect()
         + "dp_select_value" struct field becomes "ap_bank_value"
       - Remove duplicate AP cache init paths ... only use dap_ap_select(),
       and don't make Cortex (A8 or M3) cores roll their own code.
       - For dap_ap_bankselect(), pass up any fault code from writing
       the SELECT register.  (Nothing yet checks those codes.)
       - Add various bits of Doxygen
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      ARM: keep a handle to the PC · 1aac72d2
      David Brownell authored
      Keep a handle to the PC in "struct arm", and use it.
      This register is used a fair amount, so this is a net
      minor code shrink (other than some line length fixes),
      but mostly it's to make things more readable.
      For XScale, fix a dodgy sequence while stepping.  It
      was initializing a variable to a non-NULL value, then
      updating it to handle the step-over-active-breakpoint
      case, and then later testing for non-NULL to see if
      it should reverse that step-over-active logic.  It
      should have done like ARM7/ARM9 does: init to NULL.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      ARMv7-M: start using "struct arm" · ce1feaa7
      David Brownell authored
      This sets up a few of the core "struct arm" data structures so they
      can be used with ARMv7-M cores.  Specifically, it:
       - defines new ARM core_modes to match the microcontroller modes
         (e.g. HANDLER not IRQ, and two types of thread mode);
       - Establishes a new microcontroller "core_type", which can be
         used to make sure v7-M (and v6-M) cores are handled right;
       - adds "struct arm" to "struct armv7m" and arranges for the
         target_to_armv7m() converter to use it;
       - sets up the arm.core_cache and arm.cpsr values
       - makes the Cortex-M3 code maintain arm.map and arm.core_mode.
      This is currently set up as a parallel data structure, primarily to
      minimize special cases for the semihosting support with microcontroller
      profile cores.
      Later patches can rip out the duplicative ARMv7-M support and start
      reusing core ARM code.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  4. 29 Jan, 2010 1 commit
    • David Brownell's avatar
      ADIv5: cleanup, rename swjdp_transaction_endcheck() · 3d3128a8
      David Brownell authored
      Make messages reference "DAP" if they're actually transport-agnostic, or
      "JTAG-DP" when they're JTAG-specific.  Saying SWJ-DP is often wrong (on
      most Cortex-A8 chips) and is confusing even if correct (since we don't
      yet support SWD).
      Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight
      that it's JTAG-specific, and that identify DAP clients undesirably depending
      on JTAG.  (They will all need to change for SWD support.)
      Shrink a few overlong lines of code.  Copy a comment from code removed
      in a previous patch (for the ARMv7-M "dap baseaddr" command).
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  5. 27 Jan, 2010 1 commit
    • David Brownell's avatar
      Cortex-M3: report lockup, and recover · 3172be80
      David Brownell authored
      ARMv7-M defines a "lockup" state that's entered in certain double
      fault sequences which can't be recovered from without external help.
      OpenOCD has previously ignored this.
      Issue a diagnostic saying the chip has locked up, and force exit
      from this state by halting the core.  It's not clear this is the
      best way to handle lockup; but there should now be less confusion.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  6. 20 Jan, 2010 2 commits
  7. 13 Jan, 2010 1 commit
    • David Brownell's avatar
      Cortex-M3: improved core exception handling · d91941d5
      David Brownell authored
      This updates three aspects of debugger/exception interactions:
       - Save the user's "vector_catch" setting, and restore it after reset.
         Previously, it was obliterated (rather annoyingly) each time.
       - Don't catch BusFault and HardFault exceptions unless the user says
         to do so.  Target firmware may need to handle them.
       - Don't modify SHCSR to prevent escalating BusFault to HardFault.
         Target firmware may expect to handle it as a HardFault.
      Those simplifications fix several bugs.  In one annoying case, OpenOCD
      would cause the target to lock up on ome faults which triggered after
      the debugger disconnected.
      NOTE:  a known remaining issue is that OpenOCD can still leave DEMCR
      set after an otherwise-clean OpenOCD shutdown.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  8. 08 Jan, 2010 1 commit
    • David Brownell's avatar
      ARMv7: help/usage updates · 17921f51
      David Brownell authored
      Provide helptext which was sometimes missing; update some of it
      to be more accurate.
      Usage syntax messages have the same EBNF as the User's Guide;
      there should be no angle brackets in either place.
      Don't use "&function"; functions are like arrays, their address
      is their name.  Shrink some overlong lines, remove some empties.
      Add a couple comments about things that should change:  those
      extra TCK cycles for MEM-AP reads are in the wrong place (that
      might explain some problems we've seen); the DAP command tables
      should be shared, not copied.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  9. 02 Jan, 2010 2 commits
    • David Brownell's avatar
      Cortex-M3: minor breakpoint cleanup · ec88ccc5
      David Brownell authored
      Shrink some lines, add some comments, simplify some tests.
      During debug startup, log the core revision level too.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      streamline and document helptext mode displays · b3bf1d12
      David Brownell authored
      Most commands are usable only at runtime; so don't bother saying
      that, it's noise.  Moreover, tokens like EXEC are cryptic.  Be
      more clear: highlight only the commands which may (also) be used
      during the config stage, thus matching the docs more closely.
      There are
       - Configuration commands (per documentation)
       - And also some commands that valid at *any* time.
      Update the docs to note that "help" now shows this mode info.
      This also highlighted a few mistakes in command configuration,
      mostly commands listed as "valid at any time" which shouldn't
      have been.  This just fixes ones I noted when sanity testing.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  10. 21 Dec, 2009 1 commit
  11. 08 Dec, 2009 1 commit
  12. 07 Dec, 2009 2 commits
    • David Brownell's avatar
      ARM: list number of HW breakpoints/watchpoints · 81aec6be
      David Brownell authored
      When starting up, say how many hardware breakpoints and watchpoints
      are available on various targets.
      This makes it easier to tell GDB how many of those resources exist.
      Its remote protocol currently has no way to ask OpenOCD for that
      information, so it must configured by hand (or not at all).
      Update the docs to mention this; remove obsolete "don't do this" info.
      Presentation of GDB setup information is still a mess, but at least
      it calls out the three components that need setup.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      ARM: move opcode macros to <target/arm_opcodes.h> · a4a2808c
      David Brownell authored
      Move the ARM opcode macros from <target/armv4_5.h>, and a few
      Thumb2 ones from <target/armv7m.h>, to more appropriate homes
      in a new <target/arm_opcodes.h> file.
      Removed duplicate opcodes from that v7m/Thumb2 set.  Protected
      a few macro argument references by adding missing parentheses.
      Tightening up some of the line lengths turned up a curious artifact:
      the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
      There's currently no explanation for why it's done that way...
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  13. 28 Nov, 2009 2 commits
    • David Brownell's avatar
      Cortex-M3: don't chain "struct arm" commands · a398c85d
      David Brownell authored
      Those commands presume support for the "classic" set of CPU
      modes (FIQ, supervisor, IRQ, etc) ... which aren't supported
      by the ARMv7-M or ARMv6-M architectures.  They also presume
      a "struct arm" base type, which this code doesn't use.
      We haven't cleaned up the register handling enough to be able
      to share any of those "base" methods.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
    • David Brownell's avatar
      target: uplevel add_{break,watch}point() error checks · acbe054a
      David Brownell authored
      In target_type.h it's documented that the target must be
      halted for add_breakpoint() ... and with slight ambiguity,
      also for its add_watchpoint() sibling.  So rather than
      verifying that constraint in the CPU drivers, do it in the
      target_add_{break,watch}point() routines.
      Add minor paranoia on the remove_*point() paths too:  save
      the return value, and print it out in in the LOG_DEBUG message
      in case it's nonzero.
      Note that with some current cores, like all ARMv7 ones I've
      looked at, there's no technical issue preventing watchpoint or
      breakpoint add/remove operations on active cores.  This model
      seems deeply wired into OpenOCD though.
      ALSO:  the ARM targets were fairly "good" about enforcing that
      constraint themselves.  The MIPS ones were relied on other code
      to catch such stuff, but it's not clear such code existed ...
      keep an eye out for new issues on MIPS.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  14. 25 Nov, 2009 3 commits
  15. 20 Nov, 2009 1 commit
  16. 18 Nov, 2009 2 commits
    • Zachary T Welch's avatar
      use COMMAND_PARSE_ON_OFF where appropriate · 75a37eb5
      Zachary T Welch authored
      Updates all command parsing of "on" and "off" arguments.
    • David Brownell's avatar
      ARM: only use one set of dummy FPA registers · d6c89456
      David Brownell authored
      All ARM cores need to provide obsolete FPA registers in their
      GDB register dumps.  (Even though cores with floating point
      support now generally use some version of VFP...)
      Clean up that support a bit by sharing the same dummy registers,
      and removing the duplicate copies.  Eventually we shouldn't need
      to export those dummies.
      (This makes the ARMv7-M support include the armv4_5 header, and
      cleans up related #includes, but doesn't yet use anything from
      there except those dummies.)
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
  17. 17 Nov, 2009 5 commits
  18. 16 Nov, 2009 3 commits
  19. 13 Nov, 2009 4 commits