1. 22 Feb, 2010 4 commits
  2. 21 Feb, 2010 15 commits
    • David Brownell's avatar
      ADIv5: relocate memacess_tck cycles · c8ea748d
      David Brownell authored
      
      
      When using an AP to access a memory (or a memory-mapped register),
      some extra TCK (assuming JTAG) cycles should be added to ensure
      the AP has enugh time to complete that access before trying to
      collect the response.
      
      The previous code was adding these cycles *before* trying to
      access (read or write) data to that address, not *after*.  Fix
      by putting the delays in the right location.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      c8ea748d
    • David Brownell's avatar
      ADIv5: remove ATOMIC/COMPOSITE interface mode · 3b68a708
      David Brownell authored
      
      
      This removes context-sensitivity from the programming interface and makes
      it possible to know what a block of code does without needing to know the
      previous history (specifically, the DAP's "trans_mode" setting).
      
      The mode was only set to ATOMIC briefly after DAP initialization, making
      this patch be primarily cleanup; almost everything depends on COMPOSITE.
      The transactions which shouldn't have been queued were already properly
      flushing the queue.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      3b68a708
    • David Brownell's avatar
      ARM: ADIv5, deadcode cleanup · ecff7304
      David Brownell authored
      
      
      I have no idea what the scan_inout_check() was *expecting* to achieve by
      issuing a read of the DP_RDBUFF register.  But in any case, that code was
      clearly never being called ("invalue" always NULL) ... so remove it, and
      the associated comment.
      
      Also rename it as ap_write_check(), facilitating a cleanup of its single
      call site by removing constant parameters.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      ecff7304
    • David Brownell's avatar
      ARM: ADIv5 code shrinkage, cleanup · 39cfe627
      David Brownell authored
      
      
      adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing
      code duplication.  Include doxygen for the former.  Comment
      some particularly relevant points.  Minor fault handling fixes
      for both routines:  don't register a callback that can't run,
      or return ERROR_OK after an error.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      39cfe627
    • David Brownell's avatar
      ADIv5 clean up AP fault handling · a97bb675
      David Brownell authored
      
      
      Pass up fault codes from various routines, so their callers
      can clean up after failures, and remove the FIXME comments
      highlighting those previously goofy code paths.
      
       dap_ap_{read,write}_reg_u32()
       dap_ap_write_reg()
       mem_ap_{read,write}_u32()
       mem_ap_{read,write}_atomic_u32()
       dap_setup_accessport()
      
      Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(),
      instead of cloning its core code (and broken fault handling).
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a97bb675
    • David Brownell's avatar
      ADIv5 clean up AP selection and register caching · 249263d2
      David Brownell authored
      
      
      Handling of AP (and AP register bank) selection, and cached AP
      registers, is pretty loose ... start tightening it:
      
       - It's "AP bank" select support ... there are no DP banks.  Rename.
         + dap_dp_bankselect() becomes dap_ap_bankselect()
         + "dp_select_value" struct field becomes "ap_bank_value"
      
       - Remove duplicate AP cache init paths ... only use dap_ap_select(),
       and don't make Cortex (A8 or M3) cores roll their own code.
      
       - For dap_ap_bankselect(), pass up any fault code from writing
       the SELECT register.  (Nothing yet checks those codes.)
      
       - Add various bits of Doxygen
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      249263d2
    • David Brownell's avatar
      ARM: keep a handle to the PC · 1aac72d2
      David Brownell authored
      
      
      Keep a handle to the PC in "struct arm", and use it.
      This register is used a fair amount, so this is a net
      minor code shrink (other than some line length fixes),
      but mostly it's to make things more readable.
      
      For XScale, fix a dodgy sequence while stepping.  It
      was initializing a variable to a non-NULL value, then
      updating it to handle the step-over-active-breakpoint
      case, and then later testing for non-NULL to see if
      it should reverse that step-over-active logic.  It
      should have done like ARM7/ARM9 does: init to NULL.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      1aac72d2
    • David Brownell's avatar
      ARM DPM: support adding/removing HW breakpoints · a299371a
      David Brownell authored
      
      
      Generalize the core of watchpoint setup so that it can handle
      breakpoints too.  Create breakpoint add/remove routines which
      will use that, and hook them up to target types which don't
      provide their own breakpoint support (nothing, yet).
      
      This suffices for hardware-only breakpoint support.  The ARM11
      code will be able to switch over to this without much trouble,
      since it doesn't yet handle software breakpoints.  Switching
      Cortex-A8 will be a bit more involved.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a299371a
    • David Brownell's avatar
      ARM11: per-core options should not be global · 27c068c1
      David Brownell authored
      
      
      Address some FIXME comments by getting rid of globals, moving
      per-core parameters in the existing per-core data structure.
      
      This will matter most whenever there are multiple ARM11 cores,
      e.g. ARM11 MPcore chips, but in general is just cleanup.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      27c068c1
    • David Brownell's avatar
      ARMv7-M: start using "struct arm" · ce1feaa7
      David Brownell authored
      
      
      This sets up a few of the core "struct arm" data structures so they
      can be used with ARMv7-M cores.  Specifically, it:
      
       - defines new ARM core_modes to match the microcontroller modes
         (e.g. HANDLER not IRQ, and two types of thread mode);
      
       - Establishes a new microcontroller "core_type", which can be
         used to make sure v7-M (and v6-M) cores are handled right;
      
       - adds "struct arm" to "struct armv7m" and arranges for the
         target_to_armv7m() converter to use it;
      
       - sets up the arm.core_cache and arm.cpsr values
      
       - makes the Cortex-M3 code maintain arm.map and arm.core_mode.
      
      This is currently set up as a parallel data structure, primarily to
      minimize special cases for the semihosting support with microcontroller
      profile cores.
      
      Later patches can rip out the duplicative ARMv7-M support and start
      reusing core ARM code.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      ce1feaa7
    • David Brownell's avatar
    • David Brownell's avatar
      56e74908
    • David Brownell's avatar
      User's Guide mentions OS-specific installation · 4aa0a4d8
      David Brownell authored
      
      
      Specifically the Linux issue of needing "udev" rules, and MS-Windows
      needing driver configuration.
      
      Also, update the existing udev note to use the correct name of that
      rules file in the source tree.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      4aa0a4d8
    • David Brownell's avatar
      arm920t line length cleanup · bb4cb793
      David Brownell authored
      
      
      The recent patch to fixbreakpoints and dcache handling added
      a bunch of overlong lines (80+ chars) ... shrink them, and do
      the same to a few lines which were already overlong.
      
      Also add a few FIXME comments to nudge (a) replacement of some
      magic numbers with opcode macros, which will be much better at
      showing what's actually going on, and (b) correct return codes.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      bb4cb793
    • David Brownell's avatar
      CSB337 board cleanup (quasi-regression) · 57d5673d
      David Brownell authored
      
      
      Get rid of new nasty warning:
      
      NOTE! Severe performance degradation without fast memory access enabled...
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      57d5673d
  3. 20 Feb, 2010 1 commit
  4. 19 Feb, 2010 1 commit
    • Marc Pignat's avatar
      atm920t : fix breakpoints and data cache handling · 3f30563c
      Marc Pignat authored
      Breakpoints did not work because the data cache was not flushed
      properly.
      
      As a bonus add capability to write to memory marked as read only
      by the MMU, which allows software breakpoints in such memory
      regions.
      3f30563c
  5. 17 Feb, 2010 1 commit
    • David Brownell's avatar
      ARM920T scanchain 15 comments/cleanup · aa8db989
      David Brownell authored
      
      
      For folk who don't know the ARM920 JTAG interface very well, the
      two modes of scan chain 15 access to CP15 are confusing.
      
      Make those parts of the ARM920 code less opaque, by:
      
       - Adding comments referencing the relevant parts of the TRM,
         catching up to similar updates in the User's Guide.
      
       - Replacing magic numbers in physical access clients with
         symbolic equivalents.
      
      No functional change.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      aa8db989
  6. 15 Feb, 2010 2 commits
  7. 14 Feb, 2010 2 commits
    • Mathias Kuester's avatar
      fix crash with DSP563XX · 52d4ba34
      Mathias Kuester authored
      
      
      When a DSP563xx-aware GDB asks OpenOCD for target registers,
      the result should be a GDB with register data ... not an
      OpenOCD crash.
      
      (Note that mainline GDB doesn't currently support this core,
      so for now, this requires a GDB with FreeScale patches.)
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      52d4ba34
    • David Brownell's avatar
      NEWS: mention removal of obsolete commands · a2ce3a51
      David Brownell authored
      
      
      Removed remaining support for various commands, like advice for
      migrating old-style TAP declarations.
      
      The documentation no longer describes them either ... so if users have
      been delaying config updates, they may need to consult older releases.
      
      ALL this stuff has been clearly marked as "do not use" for at least a
      year now, so anyone still using it hasn't been holding up their end.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      a2ce3a51
  8. 13 Feb, 2010 2 commits
  9. 12 Feb, 2010 4 commits
  10. 11 Feb, 2010 2 commits
  11. 10 Feb, 2010 2 commits
  12. 09 Feb, 2010 2 commits
  13. 07 Feb, 2010 2 commits
    • David Brownell's avatar
      Re-title Developer's Guide · 885a2f5b
      David Brownell authored
      
      
      The Doxygen output was previously titled "OpenOCD Reference Manual",
      which was quite misleading ... the User's Guide is the reference
      manual which folk should consult about how to use the software.
      
      Just rename it to match how it's been discussed previously, and to
      bring out its intended audience:  developers of this software.  As a
      rule, Doxygen is only for folk who work with the code it documents.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      885a2f5b
    • David Brownell's avatar
      ADIv5: doxygen · 6f262b69
      David Brownell authored
      
      
      Provide doxygen for many of the public ADIv5 interfaces (i.e. the ones
      called from Cortex core support code).
      
      Add FIXMEs (and a TODO) to help resolve implementation issues which
      became more apparent when trying to document this code:
      
       - Error-prone context-sensitivity (queued/nonqueued) in many procedures.
      
       - Procedures that lie by ignoring errors and wrongly claiming success.
      
      Also, there was no point in a return from dap_ap_select(); it can't fail,
      and no caller checks its return status.  Clean that up, make it void.
      Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
      6f262b69