Commit fb1a9b2c authored by zwelch's avatar zwelch
Browse files

- Fixes '[|]' whitespace

- Replace ')\([|]\)(' with ') \1 ('.
- Replace ')\([|]\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\([|]\)(' with '\1 \2 ('.
- Replace '\(\w\)\([|]\)\(\w\)' with '\1 \2 \3'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2374 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 8959de9f
...@@ -1460,7 +1460,7 @@ static int logfs_fo_close(struct CYG_FILE_TAG *fp); ...@@ -1460,7 +1460,7 @@ static int logfs_fo_close(struct CYG_FILE_TAG *fp);
// For simplicity we use _FILESYSTEM synchronization for all accesses since // For simplicity we use _FILESYSTEM synchronization for all accesses since
// we should never block in any filesystem operations. // we should never block in any filesystem operations.
FSTAB_ENTRY( logfs_fste, "logfs", 0, FSTAB_ENTRY( logfs_fste, "logfs", 0,
CYG_SYNCMODE_FILE_FILESYSTEM|CYG_SYNCMODE_IO_FILESYSTEM, CYG_SYNCMODE_FILE_FILESYSTEM | CYG_SYNCMODE_IO_FILESYSTEM,
logfs_mount, logfs_mount,
logfs_umount, logfs_umount,
logfs_open, logfs_open,
......
...@@ -107,7 +107,7 @@ static int at91sam7_register_commands(struct command_context_s *cmd_ctx) ...@@ -107,7 +107,7 @@ static int at91sam7_register_commands(struct command_context_s *cmd_ctx)
command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL); command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC, register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
"at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit"); "at91sam7 gpnvm <bit> set | clear, set or clear one gpnvm bit");
return ERROR_OK; return ERROR_OK;
} }
...@@ -284,7 +284,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16 ...@@ -284,7 +284,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
target_write_u32(target, MC_FCR[bank->bank_number], fcr); target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen); LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB)|(cmd == CLB))) if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB)))
{ {
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */ /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C) if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
...@@ -1138,7 +1138,7 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char ...@@ -1138,7 +1138,7 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char
if (argc != 2) if (argc != 2)
{ {
command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set|clear>"); command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set | clear>");
return ERROR_OK; return ERROR_OK;
} }
......
...@@ -197,7 +197,7 @@ int flash_init_drivers(struct command_context_s *cmd_ctx) ...@@ -197,7 +197,7 @@ int flash_init_drivers(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, flash_cmd, "write_image", handle_flash_write_image_command, COMMAND_EXEC, register_command(cmd_ctx, flash_cmd, "write_image", handle_flash_write_image_command, COMMAND_EXEC,
"write_image [erase] <file> [offset] [type]"); "write_image [erase] <file> [offset] [type]");
register_command(cmd_ctx, flash_cmd, "protect", handle_flash_protect_command, COMMAND_EXEC, register_command(cmd_ctx, flash_cmd, "protect", handle_flash_protect_command, COMMAND_EXEC,
"set protection of sectors at <bank> <first> <last> <on|off>"); "set protection of sectors at <bank> <first> <last> <on | off>");
} }
return ERROR_OK; return ERROR_OK;
......
...@@ -30,18 +30,18 @@ ...@@ -30,18 +30,18 @@
/* flash programming support for Philips LPC2xxx devices /* flash programming support for Philips LPC2xxx devices
* currently supported devices: * currently supported devices:
* variant 1 (lpc2000_v1): * variant 1 (lpc2000_v1):
* - 2104|5|6 * - 2104 | 5|6
* - 2114|9 * - 2114 | 9
* - 2124|9 * - 2124 | 9
* - 2194 * - 2194
* - 2212|4 * - 2212 | 4
* - 2292|4 * - 2292 | 4
* *
* variant 2 (lpc2000_v2): * variant 2 (lpc2000_v2):
* - 213x * - 213x
* - 214x * - 214x
* - 2101|2|3 * - 2101 | 2|3
* - 2364|6|8 * - 2364 | 6|8
* - 2378 * - 2378
*/ */
......
...@@ -311,9 +311,9 @@ int nand_init(struct command_context_s *cmd_ctx) ...@@ -311,9 +311,9 @@ int nand_init(struct command_context_s *cmd_ctx)
"erase blocks on NAND flash device <num> <offset> <length>"); "erase blocks on NAND flash device <num> <offset> <length>");
register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC, register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
"dump from NAND flash device <num> <filename> " "dump from NAND flash device <num> <filename> "
"<offset> <length> [oob_raw|oob_only]"); "<offset> <length> [oob_raw | oob_only]");
register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC, register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
"write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc|oob_softecc_kw]"); "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC, register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
"raw access to NAND flash device <num> ['enable'|'disable']"); "raw access to NAND flash device <num> ['enable'|'disable']");
} }
......
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#define KB 1024 #define KB 1024
#define MB (1024*1024) #define MB (1024*1024)
#define ERASE_REGION(num, size) (((size/256) << 16)|(num-1)) #define ERASE_REGION(num, size) (((size/256) << 16) | (num-1))
/* non-CFI compatible flashes */ /* non-CFI compatible flashes */
non_cfi_t non_cfi_flashes[] = { non_cfi_t non_cfi_flashes[] = {
......
...@@ -72,7 +72,7 @@ void cmd_flash(uint32 cmd) ...@@ -72,7 +72,7 @@ void cmd_flash(uint32 cmd)
/* verify written data */ /* verify written data */
if (!result) result = flash_verify(adr, len, ((uint8 *)buffer) + ofs); if (!result) result = flash_verify(adr, len, ((uint8 *)buffer) + ofs);
dcc_wr(OCL_CMD_DONE|result); dcc_wr(OCL_CMD_DONE | result);
} }
...@@ -84,14 +84,14 @@ int main (void) ...@@ -84,14 +84,14 @@ int main (void)
cmd = dcc_rd(); cmd = dcc_rd();
switch (cmd&OCL_CMD_MASK) { switch (cmd&OCL_CMD_MASK) {
case OCL_PROBE: case OCL_PROBE:
dcc_wr(OCL_CMD_DONE|flash_init()); dcc_wr(OCL_CMD_DONE | flash_init());
dcc_wr(0x100000); /* base */ dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */ dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */ dcc_wr(1); /* num_sectors */
dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */ dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
break; break;
case OCL_ERASE_ALL: case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE|flash_erase_all()); dcc_wr(OCL_CMD_DONE | flash_erase_all());
break; break;
case OCL_FLASH_BLOCK: case OCL_FLASH_BLOCK:
cmd_flash(cmd); cmd_flash(cmd);
......
...@@ -164,7 +164,7 @@ int flash_erase_plane(int efc_ofs) ...@@ -164,7 +164,7 @@ int flash_erase_plane(int efc_ofs)
if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE; if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
/* set no erase before programming */ /* set no erase before programming */
outr(MC_FMR + efc_ofs, inr(MC_FMR + efc_ofs)|0x80); outr(MC_FMR + efc_ofs, inr(MC_FMR + efc_ofs) | 0x80);
return FLASH_STAT_OK; return FLASH_STAT_OK;
} }
......
...@@ -162,7 +162,7 @@ static int pic32mx_nvm_exec(struct flash_bank_s *bank, uint32_t op, uint32_t tim ...@@ -162,7 +162,7 @@ static int pic32mx_nvm_exec(struct flash_bank_s *bank, uint32_t op, uint32_t tim
target_t *target = bank->target; target_t *target = bank->target;
uint32_t status; uint32_t status;
target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN|op); target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
/* unlock flash registers */ /* unlock flash registers */
target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1); target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
...@@ -841,7 +841,7 @@ static int pic32mx_chip_erase(struct flash_bank_s *bank) ...@@ -841,7 +841,7 @@ static int pic32mx_chip_erase(struct flash_bank_s *bank)
/* chip erase flash memory */ /* chip erase flash memory */
target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER); target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER|FLASH_STRT); target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER | FLASH_STRT);
status = pic32mx_wait_status_busy(bank, 10); status = pic32mx_wait_status_busy(bank, 10);
......
...@@ -346,7 +346,7 @@ static uint32_t stellaris_get_flash_status(flash_bank_t *bank) ...@@ -346,7 +346,7 @@ static uint32_t stellaris_get_flash_status(flash_bank_t *bank)
target_t *target = bank->target; target_t *target = bank->target;
uint32_t fmc; uint32_t fmc;
target_read_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, &fmc); target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc);
return fmc; return fmc;
} }
...@@ -360,9 +360,9 @@ static void stellaris_read_clock_info(flash_bank_t *bank) ...@@ -360,9 +360,9 @@ static void stellaris_read_clock_info(flash_bank_t *bank)
uint32_t rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc; uint32_t rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
unsigned long mainfreq; unsigned long mainfreq;
target_read_u32(target, SCB_BASE|RCC, &rcc); target_read_u32(target, SCB_BASE | RCC, &rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc); LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg); target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg); LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
stellaris_info->rcc = rcc; stellaris_info->rcc = rcc;
...@@ -412,7 +412,7 @@ static void stellaris_set_flash_mode(flash_bank_t *bank,int mode) ...@@ -412,7 +412,7 @@ static void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1); uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
LOG_DEBUG("usecrl = %i",(int)(usecrl)); LOG_DEBUG("usecrl = %i",(int)(usecrl));
target_write_u32(target, SCB_BASE|USECRL, usecrl); target_write_u32(target, SCB_BASE | USECRL, usecrl);
} }
#if 0 #if 0
...@@ -439,7 +439,7 @@ static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,uint16_ ...@@ -439,7 +439,7 @@ static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,uint16_
target_t *target = bank->target; target_t *target = bank->target;
fmc = FMC_WRKEY | cmd; fmc = FMC_WRKEY | cmd;
target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc); target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc);
LOG_DEBUG("Flash command: 0x%x", fmc); LOG_DEBUG("Flash command: 0x%x", fmc);
if (stellaris_wait_status_busy(bank, cmd, 100)) if (stellaris_wait_status_busy(bank, cmd, 100))
...@@ -460,10 +460,10 @@ static int stellaris_read_part_info(struct flash_bank_s *bank) ...@@ -460,10 +460,10 @@ static int stellaris_read_part_info(struct flash_bank_s *bank)
int i; int i;
/* Read and parse chip identification register */ /* Read and parse chip identification register */
target_read_u32(target, SCB_BASE|DID0, &did0); target_read_u32(target, SCB_BASE | DID0, &did0);
target_read_u32(target, SCB_BASE|DID1, &did1); target_read_u32(target, SCB_BASE | DID1, &did1);
target_read_u32(target, SCB_BASE|DC0, &stellaris_info->dc0); target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
target_read_u32(target, SCB_BASE|DC1, &stellaris_info->dc1); target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "", LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
did0, did1, stellaris_info->dc0, stellaris_info->dc1); did0, did1, stellaris_info->dc0, stellaris_info->dc1);
...@@ -503,7 +503,7 @@ static int stellaris_read_part_info(struct flash_bank_s *bank) ...@@ -503,7 +503,7 @@ static int stellaris_read_part_info(struct flash_bank_s *bank)
stellaris_info->pagesize = 1024; stellaris_info->pagesize = 1024;
bank->size = 1024 * stellaris_info->num_pages; bank->size = 1024 * stellaris_info->num_pages;
stellaris_info->pages_in_lockregion = 2; stellaris_info->pages_in_lockregion = 2;
target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits); target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
/* provide this for the benefit of the higher flash driver layers */ /* provide this for the benefit of the higher flash driver layers */
bank->num_sectors = stellaris_info->num_pages; bank->num_sectors = stellaris_info->num_pages;
...@@ -597,7 +597,7 @@ static int stellaris_erase(struct flash_bank_s *bank, int first, int last) ...@@ -597,7 +597,7 @@ static int stellaris_erase(struct flash_bank_s *bank, int first, int last)
/* Clear and disable flash programming interrupts */ /* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC); target_write_u32(target, FLASH_MISC, PMISC | AMISC);
for (banknr = first; banknr <= last; banknr++) for (banknr = first; banknr <= last; banknr++)
{ {
...@@ -672,10 +672,10 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int ...@@ -672,10 +672,10 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int
/* Clear and disable flash programming interrupts */ /* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC); target_write_u32(target, FLASH_MISC, PMISC | AMISC);
LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe); LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
target_write_u32(target, SCB_BASE|FMPPE, fmppe); target_write_u32(target, SCB_BASE | FMPPE, fmppe);
/* Commit FMPPE */ /* Commit FMPPE */
target_write_u32(target, FLASH_FMA, 1); target_write_u32(target, FLASH_FMA, 1);
/* Write commit command */ /* Write commit command */
...@@ -698,7 +698,7 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int ...@@ -698,7 +698,7 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;
} }
target_read_u32(target, SCB_BASE|FMPPE, &stellaris_info->lockbits); target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
return ERROR_OK; return ERROR_OK;
} }
...@@ -869,7 +869,7 @@ static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t ...@@ -869,7 +869,7 @@ static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t
/* Clear and disable flash programming interrupts */ /* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC); target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* multiple words to be programmed? */ /* multiple words to be programmed? */
if (words_remaining > 0) if (words_remaining > 0)
...@@ -1014,7 +1014,7 @@ static int stellaris_mass_erase(struct flash_bank_s *bank) ...@@ -1014,7 +1014,7 @@ static int stellaris_mass_erase(struct flash_bank_s *bank)
/* Clear and disable flash programming interrupts */ /* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC); target_write_u32(target, FLASH_MISC, PMISC | AMISC);
target_write_u32(target, FLASH_FMA, 0); target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE); target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
......
...@@ -68,12 +68,12 @@ typedef struct stellaris_flash_bank_s ...@@ -68,12 +68,12 @@ typedef struct stellaris_flash_bank_s
#define USECRL 0x140 #define USECRL 0x140
#define FLASH_CONTROL_BASE 0x400FD000 #define FLASH_CONTROL_BASE 0x400FD000
#define FLASH_FMA (FLASH_CONTROL_BASE|0x000) #define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
#define FLASH_FMD (FLASH_CONTROL_BASE|0x004) #define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
#define FLASH_FMC (FLASH_CONTROL_BASE|0x008) #define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
#define FLASH_CRIS (FLASH_CONTROL_BASE|0x00C) #define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
#define FLASH_CIM (FLASH_CONTROL_BASE|0x010) #define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
#define FLASH_MISC (FLASH_CONTROL_BASE|0x014) #define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
#define AMISC 1 #define AMISC 1
#define PMISC 2 #define PMISC 2
......
...@@ -122,9 +122,9 @@ static uint32_t stm32x_wait_status_busy(flash_bank_t *bank, int timeout) ...@@ -122,9 +122,9 @@ static uint32_t stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
alive_sleep(1); alive_sleep(1);
} }
/* Clear but report errors */ /* Clear but report errors */
if (status & (FLASH_WRPRTERR|FLASH_PGERR)) if (status & (FLASH_WRPRTERR | FLASH_PGERR))
{ {
target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR|FLASH_PGERR); target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
} }
return status; return status;
} }
...@@ -140,7 +140,7 @@ static int stm32x_read_options(struct flash_bank_s *bank) ...@@ -140,7 +140,7 @@ static int stm32x_read_options(struct flash_bank_s *bank)
/* read current option bytes */ /* read current option bytes */
target_read_u32(target, STM32_FLASH_OBR, &optiondata); target_read_u32(target, STM32_FLASH_OBR, &optiondata);
stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8|((optiondata >> 2) & 0x07); stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5; stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
if (optiondata & (1 << OPT_READOUT)) if (optiondata & (1 << OPT_READOUT))
...@@ -177,8 +177,8 @@ static int stm32x_erase_options(struct flash_bank_s *bank) ...@@ -177,8 +177,8 @@ static int stm32x_erase_options(struct flash_bank_s *bank)
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* erase option bytes */ /* erase option bytes */
target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE); target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE); target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
status = stm32x_wait_status_busy(bank, 10); status = stm32x_wait_status_busy(bank, 10);
...@@ -211,7 +211,7 @@ static int stm32x_write_options(struct flash_bank_s *bank) ...@@ -211,7 +211,7 @@ static int stm32x_write_options(struct flash_bank_s *bank)
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* program option bytes */ /* program option bytes */
target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE); target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
/* write user option byte */ /* write user option byte */
target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options); target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
...@@ -374,7 +374,7 @@ static int stm32x_erase(struct flash_bank_s *bank, int first, int last) ...@@ -374,7 +374,7 @@ static int stm32x_erase(struct flash_bank_s *bank, int first, int last)
{ {
target_write_u32(target, STM32_FLASH_CR, FLASH_PER); target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset); target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT); target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10); status = stm32x_wait_status_busy(bank, 10);
...@@ -1098,7 +1098,7 @@ static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx ...@@ -1098,7 +1098,7 @@ static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx
if (argc < 4) if (argc < 4)
{ {
command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>"); command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
return ERROR_OK; return ERROR_OK;
} }
...@@ -1182,7 +1182,7 @@ static int stm32x_mass_erase(struct flash_bank_s *bank) ...@@ -1182,7 +1182,7 @@ static int stm32x_mass_erase(struct flash_bank_s *bank)
/* mass erase flash memory */ /* mass erase flash memory */
target_write_u32(target, STM32_FLASH_CR, FLASH_MER); target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT); target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10); status = stm32x_wait_status_busy(bank, 10);
......
...@@ -160,7 +160,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd ...@@ -160,7 +160,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
bank->driver_priv = str7x_info; bank->driver_priv = str7x_info;
/* set default bits for str71x flash */ /* set default bits for str71x flash */
str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA1|FLASH_BSYA0); str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
str7x_info->disable_bit = (1 << 1); str7x_info->disable_bit = (1 << 1);
if (strcmp(args[6], "STR71x") == 0) if (strcmp(args[6], "STR71x") == 0)
...@@ -170,7 +170,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd ...@@ -170,7 +170,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
else if (strcmp(args[6], "STR73x") == 0) else if (strcmp(args[6], "STR73x") == 0)
{ {
str7x_info->register_base = 0x80100000; str7x_info->register_base = 0x80100000;
str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA0); str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
} }
else if (strcmp(args[6], "STR75x") == 0) else if (strcmp(args[6], "STR75x") == 0)
{ {
...@@ -270,7 +270,7 @@ static int str7x_erase(struct flash_bank_s *bank, int first, int last) ...@@ -270,7 +270,7 @@ static int str7x_erase(struct flash_bank_s *bank, int first, int last)
cmd = sectors; cmd = sectors;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
cmd = FLASH_SER|FLASH_WMS; cmd = FLASH_SER | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){ while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
...@@ -326,7 +326,7 @@ static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last ...@@ -326,7 +326,7 @@ static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last
cmd = protect_blocks; cmd = protect_blocks;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
cmd = FLASH_SPR|FLASH_WMS; cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){ while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
......
...@@ -1002,7 +1002,7 @@ static int str9xpec_handle_flash_options_cmap_command(struct command_context_s * ...@@ -1002,7 +1002,7 @@ static int str9xpec_handle_flash_options_cmap_command(struct command_context_s *
if (argc < 2) if (argc < 2)
{ {
command_print(cmd_ctx, "str9xpec options_cmap <bank> <bank0|bank1>"); command_print(cmd_ctx, "str9xpec options_cmap <bank> <bank0 | bank1>");
return ERROR_OK; return ERROR_OK;
} }
...@@ -1034,7 +1034,7 @@ static int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s ...@@ -1034,7 +1034,7 @@ static int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s
if (argc < 2) if (argc < 2)
{ {
command_print(cmd_ctx, "str9xpec options_lvdthd <bank> <2.4v|2.7v>"); command_print(cmd_ctx, "str9xpec options_lvdthd <bank> <2.4v | 2.7v>");
return ERROR_OK; return ERROR_OK;
} }
...@@ -1066,7 +1066,7 @@ int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_c ...@@ -1066,7 +1066,7 @@ int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_c
if (argc < 2) if (argc < 2)
{ {
command_print(cmd_ctx, "str9xpec options_lvdsel <bank> <vdd|vdd_vddq>"); command_print(cmd_ctx, "str9xpec options_lvdsel <bank> <vdd | vdd_vddq>");
return ERROR_OK; return ERROR_OK;
} }
...@@ -1098,7 +1098,7 @@ static int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_ ...@@ -1098,7 +1098,7 @@ static int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_
if (argc < 2) if (argc < 2)
{ {
command_print(cmd_ctx, "str9xpec options_lvdwarn <bank> <vdd|vdd_vddq>"); command_print(cmd_ctx, "str9xpec options_lvdwarn <bank> <vdd | vdd_vddq>");
return ERROR_OK; return ERROR_OK;
} }