Commit db7c3810 authored by oharboe's avatar oharboe
Browse files

allow minidrivers to implement inner loop of dcc memory writes

git-svn-id: svn://svn.berlios.de/openocd/trunk@879 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 0f18744a
......@@ -64,13 +64,13 @@ int arm7_9_reinit_embeddedice(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = target->breakpoints;
arm7_9->wp_available = 2;
arm7_9->wp0_used = 0;
arm7_9->wp1_used = 0;
/* mark all hardware breakpoints as unset */
while (breakpoint)
{
......@@ -80,13 +80,13 @@ int arm7_9_reinit_embeddedice(target_t *target)
}
breakpoint = breakpoint->next;
}
if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
{
arm7_9->sw_bkpts_enabled = 0;
arm7_9_enable_sw_bkpts(target);
}
return ERROR_OK;
}
......@@ -104,20 +104,20 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
return -1;
}
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{
return -1;
}
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
return ERROR_OK;
}
......@@ -125,13 +125,13 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (arm7_9->force_hw_bkpts)
breakpoint->type = BKPT_HARD;
......@@ -184,7 +184,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if (verify != arm7_9->arm_bkpt)
{
......@@ -199,7 +199,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if (verify != arm7_9->thumb_bkpt)
{
......@@ -218,7 +218,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
......@@ -230,7 +230,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
if (breakpoint->type == BKPT_HARD)
{
if (breakpoint->set == 1)
......@@ -276,40 +276,40 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (arm7_9->force_hw_bkpts)
{
LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
breakpoint->type = BKPT_HARD;
}
if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
{
LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
{
LOG_INFO("no watchpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->length != 2) && (breakpoint->length != 4))
{
LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
arm7_9->wp_available--;
return ERROR_OK;
}
......@@ -317,21 +317,21 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (breakpoint->set)
{
arm7_9_unset_breakpoint(target, breakpoint);
}
if (breakpoint->type == BKPT_HARD)
arm7_9->wp_available++;
return ERROR_OK;
}
......@@ -341,20 +341,20 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int rw_mask = 1;
u32 mask;
mask = watchpoint->length - 1;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (watchpoint->rw == WPT_ACCESS)
rw_mask = 0;
else
rw_mask = 1;
if (!arm7_9->wp0_used)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
......@@ -382,13 +382,13 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
jtag_execute_queue();
watchpoint->set = 2;
arm7_9->wp1_used = 2;
}
}
else
{
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
return ERROR_OK;
}
......@@ -396,19 +396,19 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!watchpoint->set)
{
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
if (watchpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
......@@ -430,25 +430,25 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (arm7_9->wp_available < 1)
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
arm7_9->wp_available--;
return ERROR_OK;
}
......@@ -456,20 +456,20 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (watchpoint->set)
{
arm7_9_unset_watchpoint(target, watchpoint);
}
arm7_9->wp_available++;
return ERROR_OK;
}
......@@ -478,17 +478,17 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int retval;
if (arm7_9->sw_bkpts_enabled)
return ERROR_OK;
if (arm7_9->wp_available < 1)
{
LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
arm7_9->wp_available--;
if (!arm7_9->wp0_used)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
......@@ -514,13 +514,13 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
return ERROR_FAIL;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
return ERROR_FAIL;
};
return ERROR_OK;
}
......@@ -528,10 +528,10 @@ int arm7_9_disable_sw_bkpts(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (!arm7_9->sw_bkpts_enabled)
return ERROR_OK;
if (arm7_9->sw_bkpts_enabled == 1)
{
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
......@@ -554,12 +554,12 @@ int arm7_9_execute_sys_speed(struct target_s *target)
{
int timeout;
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
if (arm7_9->need_bypass_before_restart) {
......@@ -567,7 +567,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
arm_jtag_set_instr(jtag_info, 0xf, NULL);
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
for (timeout=0; timeout<50; timeout++)
{
/* read debug status register */
......@@ -577,14 +577,14 @@ int arm7_9_execute_sys_speed(struct target_s *target)
if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
&& (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
break;
usleep(100000);
usleep(100000);
}
if (timeout == 50)
{
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
......@@ -592,12 +592,12 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
static int set=0;
static u8 check_value[4], check_mask[4];
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
if (arm7_9->need_bypass_before_restart) {
......@@ -605,11 +605,11 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
arm_jtag_set_instr(jtag_info, 0xf, NULL);
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
if (!set)
{
/* check for DBGACK and SYSCOMP set (others don't care) */
/* NB! These are constants that must be available until after next jtag_execute() and
we evaluate the values upon first execution in lieu of setting up these constants
during early setup.
......@@ -618,7 +618,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
buf_set_u32(check_mask, 0, 32, 0x9);
set=1;
}
/* read debug status register */
embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
......@@ -632,18 +632,18 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 *data;
int i;
data = malloc(size * (sizeof(u32)));
embeddedice_receive(jtag_info, data, size);
for (i = 0; i < size; i++)
{
h_u32_to_le(buffer + (i * 4), data[i]);
}
free(data);
return ERROR_OK;
}
......@@ -654,29 +654,29 @@ int arm7_9_handle_target_request(void *priv)
return ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
return ERROR_OK;
if (target->state == TARGET_RUNNING)
{
/* read DCC control register */
embeddedice_read_reg(dcc_control);
jtag_execute_queue();
/* check W bit */
if (buf_get_u32(dcc_control->value, 1, 1) == 1)
{
u32 request;
embeddedice_receive(jtag_info, &request, 1);
target_request(target, request);
}
}
return ERROR_OK;
}
......@@ -693,7 +693,7 @@ int arm7_9_poll(target_t *target)
{
return retval;
}
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
{
/* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
......@@ -715,12 +715,12 @@ int arm7_9_poll(target_t *target)
}
}
}
target->state = TARGET_HALTED;
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
if (check_pc)
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
......@@ -730,7 +730,7 @@ int arm7_9_poll(target_t *target)
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
}
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
if (target->state == TARGET_DEBUG_RUNNING)
......@@ -738,7 +738,7 @@ int arm7_9_poll(target_t *target)
target->state = TARGET_HALTED;
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
if (target->state != TARGET_HALTED)
......@@ -751,7 +751,7 @@ int arm7_9_poll(target_t *target)
if (target->state != TARGET_DEBUG_RUNNING)
target->state = TARGET_RUNNING;
}
return ERROR_OK;
}
......@@ -768,7 +768,7 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
......@@ -780,9 +780,9 @@ int arm7_9_assert_reset(target_t *target)
/*
* Some targets do not support communication while SRST is asserted. We need to
* set up the reset vector catch here.
*
*
* If TRST is asserted, then these settings will be reset anyway, so setting them
* here is harmless.
* here is harmless.
*/
if (arm7_9->has_vector_catch)
{
......@@ -808,7 +808,7 @@ int arm7_9_assert_reset(target_t *target)
{
jtag_add_reset(0, 1);
}
target->state = TARGET_RESET;
jtag_add_sleep(50000);
......@@ -822,10 +822,10 @@ int arm7_9_assert_reset(target_t *target)
int arm7_9_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
return ERROR_OK;
}
......@@ -834,13 +834,13 @@ int arm7_9_clear_halt(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
{
/* program EmbeddedICE Debug Control Register to deassert DBGRQ
*/
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
embeddedice_store_reg(dbg_ctrl);
}
else
......@@ -867,13 +867,13 @@ int arm7_9_clear_halt(target_t *target)
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
}
/* control value always has to be restored, as it was either disabled,
/* control value always has to be restored, as it was either disabled,
* or enabled with possibly different bits
*/
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
}
}
return ERROR_OK;
}
......@@ -885,10 +885,10 @@ int arm7_9_soft_reset_halt(struct target_s *target)
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
int retval;
if ((retval=target_halt(target))!=ERROR_OK)
return retval;
for (i=0; i<10; i++)
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
......@@ -898,7 +898,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
return retval;
/* do not eat all CPU, time out after 1 se*/
usleep(100*1000);
}
if (i==10)
{
......@@ -906,7 +906,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
* ensure that DBGRQ is cleared
*/
......@@ -914,9 +914,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
embeddedice_store_reg(dbg_ctrl);
arm7_9_clear_halt(target);
/* if the target is in Thumb state, change to ARM state */
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
{
......@@ -926,36 +926,36 @@ int arm7_9_soft_reset_halt(struct target_s *target)
armv4_5->core_state = ARMV4_5_STATE_THUMB;