Commit d34e01f5 authored by oharboe's avatar oharboe
Browse files

search and replace usleep(1000) with alive_sleep(1) to avoid GDB timeouts.

git-svn-id: svn://svn.berlios.de/openocd/trunk@942 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent dc33cb66
......@@ -258,7 +258,7 @@ u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, i
while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
{
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
usleep(1000);
alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
......
......@@ -273,7 +273,7 @@ u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
usleep(1000);
alive_sleep(1);
}
/* mask out bit 0 (reserved) */
......@@ -333,7 +333,7 @@ int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
}
oldstatus = status;
usleep(1000);
alive_sleep(1);
} while (timeout-- > 0);
LOG_ERROR("timeout, status: 0x%x", status);
......
......@@ -138,7 +138,7 @@ u32 lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
target_t *target = bank->target;
do
{
usleep(1000);
alive_sleep(1);
timeout--;
target_read_u32(target, F_STAT, &status);
}while (((status & FS_DONE) == 0) && timeout);
......
......@@ -824,7 +824,7 @@ int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
return 1;
}
usleep(1000);
alive_sleep(1);
} while (timeout-- > 0);
return 0;
......@@ -864,7 +864,7 @@ int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
return 1;
}
usleep(1000);
alive_sleep(1);
} while (timeout-- > 0);
return 0;
......
......@@ -355,7 +355,7 @@ int nand_read_status(struct nand_device_s *device, u8 *status)
/* Send read status command */
device->controller->command(device, NAND_CMD_STATUS);
usleep(1000);
alive_sleep(1);
/* read status */
if (device->device->options & NAND_BUSWIDTH_16)
......
......@@ -138,7 +138,7 @@ int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
if (status & S3C2410_NFSTAT_BUSY)
return 1;
usleep(1000);
alive_sleep(1);
} while (timeout-- > 0);
return 0;
......
......@@ -114,7 +114,7 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout)
if (status & S3C2440_NFSTAT_READY)
return 1;
usleep(1000);
alive_sleep(1);
} while (timeout-- > 0);
......
......@@ -410,7 +410,7 @@ u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
usleep(1000);
alive_sleep(1);
}
/* Flash errors are reflected in the FLASH_CRIS register */
......
......@@ -126,7 +126,7 @@ u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
usleep(1000);
alive_sleep(1);
}
return status;
......
......@@ -283,7 +283,7 @@ int str7x_erase(struct flash_bank_s *bank, int first, int last)
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
usleep(1000);
alive_sleep(1);
}
retval = str7x_result(bank);
......@@ -339,7 +339,7 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
usleep(1000);
alive_sleep(1);
}
retval = str7x_result(bank);
......@@ -568,7 +568,7 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
usleep(1000);
alive_sleep(1);
}
retval = str7x_result(bank);
......@@ -615,7 +615,7 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
usleep(1000);
alive_sleep(1);
}
retval = str7x_result(bank);
......
......@@ -313,7 +313,7 @@ int str9x_erase(struct flash_bank_s *bank, int first, int last)
}
if( status & 0x80 )
break;
usleep(1000);
alive_sleep(1);
}
/* clear status, also clear read array */
......@@ -576,7 +576,7 @@ int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
usleep(1000);
alive_sleep(1);
}
/* clear status reg and read array */
......@@ -618,7 +618,7 @@ int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
usleep(1000);
alive_sleep(1);
}
/* clear status reg and read array */
......
......@@ -530,7 +530,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
/* wait for erase completion */
while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) {
usleep(1000);
alive_sleep(1);
}
free(buffer);
......
......@@ -372,7 +372,7 @@ int tms470_try_flash_keys(target_t * target, const u32 * key_set)
do
{
target_read_u32(target, 0xFFE8A814, &fmbptr);
usleep(1000);
alive_sleep(1);
}
while (!(fmbptr & 0x0200));
......@@ -718,7 +718,7 @@ int tms470_erase_sector(struct flash_bank_s *bank, int sector)
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
if (fmmstat & 0x0100)
{
usleep(1000);
alive_sleep(1);
}
}
while (fmmstat & 0x0100);
......@@ -932,7 +932,7 @@ int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
if (fmmstat & 0x0100)
{
usleep(1000);
alive_sleep(1);
}
}
while (fmmstat & 0x0100);
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment