Commit d0dee7cc authored by Zachary T Welch's avatar Zachary T Welch
Browse files

reg_t -> struct reg

Remove misleading typedef and redundant suffix from struct reg.
parent ac927559
......@@ -863,7 +863,7 @@ static int gdb_reg_pos(target_t *target, int pos, int len)
* The format of reg->value is little endian
*
*/
void gdb_str_to_target(target_t *target, char *tstr, reg_t *reg)
void gdb_str_to_target(target_t *target, char *tstr, struct reg *reg)
{
int i;
......@@ -917,7 +917,7 @@ void gdb_target_to_reg(target_t *target, char *tstr, int str_len, uint8_t *bin)
int gdb_get_registers_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
{
reg_t **reg_list;
struct reg **reg_list;
int reg_list_size;
int retval;
int reg_packet_size = 0;
......@@ -968,7 +968,7 @@ int gdb_get_registers_packet(struct connection *connection, target_t *target, ch
int gdb_set_registers_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
{
int i;
reg_t **reg_list;
struct reg **reg_list;
int reg_list_size;
int retval;
char *packet_p;
......@@ -1019,7 +1019,7 @@ int gdb_set_registers_packet(struct connection *connection, target_t *target, ch
free(bin_buf);
}
/* free reg_t *reg_list[] array allocated by get_gdb_reg_list */
/* free struct reg *reg_list[] array allocated by get_gdb_reg_list */
free(reg_list);
gdb_put_packet(connection, "OK", 2);
......@@ -1031,7 +1031,7 @@ int gdb_get_register_packet(struct connection *connection, target_t *target, cha
{
char *reg_packet;
int reg_num = strtoul(packet + 1, NULL, 16);
reg_t **reg_list;
struct reg **reg_list;
int reg_list_size;
int retval;
......@@ -1067,7 +1067,7 @@ int gdb_set_register_packet(struct connection *connection, target_t *target, cha
char *separator;
uint8_t *bin_buf;
int reg_num = strtoul(packet + 1, &separator, 16);
reg_t **reg_list;
struct reg **reg_list;
int reg_list_size;
int retval;
struct reg_arch_type *arch_type;
......
......@@ -248,14 +248,14 @@ enum arm11_regcache_ids
static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static reg_t arm11_gdb_dummy_fp_reg =
static struct reg arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
static reg_t arm11_gdb_dummy_fps_reg =
static struct reg arm11_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
......@@ -266,8 +266,8 @@ static int arm11_step(struct target_s *target, int current,
uint32_t address, int handle_breakpoints);
/* helpers */
static int arm11_build_reg_cache(target_t *target);
static int arm11_set_reg(reg_t *reg, uint8_t *buf);
static int arm11_get_reg(reg_t *reg);
static int arm11_set_reg(struct reg *reg, uint8_t *buf);
static int arm11_get_reg(struct reg *reg);
static void arm11_record_register_history(struct arm11_common * arm11);
static void arm11_dump_reg_changes(struct arm11_common * arm11);
......@@ -1245,14 +1245,14 @@ static int arm11_soft_reset_halt(struct target_s *target)
/* target register access for gdb */
static int arm11_get_gdb_reg_list(struct target_s *target,
struct reg_s **reg_list[], int *reg_list_size)
struct reg **reg_list[], int *reg_list_size)
{
FNC_INFO;
struct arm11_common * arm11 = target->arch_info;
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
*reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
for (size_t i = 16; i < 24; i++)
{
......@@ -1657,7 +1657,7 @@ static int arm11_run_algorithm(struct target_s *target,
// Set register parameters
for (int i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
......@@ -1742,7 +1742,7 @@ static int arm11_run_algorithm(struct target_s *target,
{
if (reg_params[i].direction != PARAM_OUT)
{
reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
......@@ -1891,7 +1891,7 @@ static int arm11_examine(struct target_s *target)
/** Load a register that is marked !valid in the register cache */
static int arm11_get_reg(reg_t *reg)
static int arm11_get_reg(struct reg *reg)
{
FNC_INFO;
......@@ -1914,7 +1914,7 @@ static int arm11_get_reg(reg_t *reg)
}
/** Change a value in the register cache */
static int arm11_set_reg(reg_t *reg, uint8_t *buf)
static int arm11_set_reg(struct reg *reg, uint8_t *buf)
{
FNC_INFO;
......@@ -1934,7 +1934,7 @@ static int arm11_build_reg_cache(target_t *target)
struct arm11_common *arm11 = target->arch_info;
NEW(struct reg_cache, cache, 1);
NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
if (arm11_regs_arch_type == -1)
......@@ -1970,7 +1970,7 @@ static int arm11_build_reg_cache(target_t *target)
for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
reg_t * r = reg_list + i;
struct reg * r = reg_list + i;
const struct arm11_reg_defs * rd = arm11_reg_defs + i;
struct arm11_reg_state * rs = arm11_reg_states + i;
......
......@@ -104,7 +104,7 @@ struct arm11_common
/** \name Shadow registers to save processor state */
/*@{*/
reg_t * reg_list; /**< target register list */
struct reg * reg_list; /**< target register list */
uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
......
......@@ -304,7 +304,7 @@ static int arm720t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
struct arm720t_common *arm720t = target_to_arm720(target);
reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
struct reg *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
.arm7_9_common.armv4_5_common;
......
......@@ -704,7 +704,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
......@@ -757,7 +757,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
......@@ -834,7 +834,7 @@ int arm7_9_handle_target_request(void *priv)
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
return ERROR_OK;
......@@ -891,7 +891,7 @@ int arm7_9_poll(target_t *target)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
embeddedice_read_reg(dbg_stat);
......@@ -931,7 +931,7 @@ int arm7_9_poll(target_t *target)
if (check_pc)
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
if (t != 0)
{
......@@ -1115,7 +1115,7 @@ int arm7_9_deassert_reset(target_t *target)
int arm7_9_clear_halt(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
......@@ -1173,8 +1173,8 @@ int arm7_9_soft_reset_halt(struct target_s *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
int retval;
......@@ -1291,7 +1291,7 @@ int arm7_9_halt(target_t *target)
}
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
target_state_name(target));
......@@ -1354,8 +1354,8 @@ int arm7_9_debug_entry(target_t *target)
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
#ifdef _DEBUG_ARM7_9_
LOG_DEBUG("-");
......@@ -1599,7 +1599,7 @@ int arm7_9_restore_context(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *reg;
struct reg *reg;
struct armv4_5_core_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
int i, j;
......@@ -1803,7 +1803,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
LOG_DEBUG("-");
......@@ -2409,7 +2409,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
uint32_t num_accesses = 0;
......
......@@ -582,7 +582,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
LOG_DEBUG("-");
......
......@@ -555,7 +555,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
{
......
......@@ -232,7 +232,7 @@ static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
static int arm926ejs_examine_debug_reason(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int debug_reason;
int retval;
......@@ -524,7 +524,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
{
......
......@@ -651,7 +651,7 @@ static void arm9tdmi_branch_resume_thumb(target_t *target)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
......@@ -860,7 +860,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
target_t *target = get_current_target(cmd_ctx);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *vector_catch;
struct reg *vector_catch;
uint32_t vector_catch_value;
/* it's uncommon, but some ARM7 chips can support this */
......
......@@ -155,19 +155,19 @@ int armv4_5_core_reg_map[7][17] =
uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t armv4_5_gdb_dummy_fp_reg =
struct reg armv4_5_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t armv4_5_gdb_dummy_fps_reg =
struct reg armv4_5_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
int armv4_5_get_core_reg(reg_t *reg)
int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
......@@ -185,7 +185,7 @@ int armv4_5_get_core_reg(reg_t *reg)
return retval;
}
int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
target_t *target = armv4_5->target;
......@@ -253,7 +253,7 @@ struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
int i;
......@@ -483,7 +483,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
return ERROR_OK;
}
int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
int armv4_5_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
......@@ -492,7 +492,7 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list
return ERROR_FAIL;
*reg_list_size = 26;
*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < 16; i++)
{
......@@ -596,7 +596,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, str
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
......@@ -669,7 +669,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, str
if (reg_params[i].direction != PARAM_OUT)
{
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
......
......@@ -177,7 +177,7 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
int armv4_5_arch_state(struct target_s *target);
int armv4_5_get_gdb_reg_list(target_t *target,
reg_t **reg_list[], int *reg_list_size);
struct reg **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
......
......@@ -167,7 +167,7 @@ int armv7a_core_reg_map[8][17] =
uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t armv7a_gdb_dummy_fp_reg =
struct reg armv7a_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7a_gdb_dummy_fp_value,
0, 1, 96, NULL, 0, NULL, 0
......
......@@ -61,14 +61,14 @@ static uint8_t armv7m_gdb_dummy_fp_value[12] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
};
static reg_t armv7m_gdb_dummy_fp_reg =
static struct reg armv7m_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
static reg_t armv7m_gdb_dummy_fps_reg =
static struct reg armv7m_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
......@@ -76,7 +76,7 @@ static reg_t armv7m_gdb_dummy_fps_reg =
#ifdef ARMV7_GDB_HACKS
uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
reg_t armv7m_gdb_dummy_cpsr_reg =
struct reg armv7m_gdb_dummy_cpsr_reg =
{
"GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
};
......@@ -178,7 +178,7 @@ char *armv7m_exception_string(int number)
return enamebuf;
}
static int armv7m_get_core_reg(reg_t *reg)
static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
......@@ -195,7 +195,7 @@ static int armv7m_get_core_reg(reg_t *reg)
return retval;
}
static int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
......@@ -279,13 +279,13 @@ int armv7m_invalidate_core_regs(target_t *target)
* hardware, so this also fakes a set of long-obsolete FPA registers that
* are not used in EABI based software stacks.
*/
int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
int armv7m_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
*reg_list_size = 26;
*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
/*
* GDB register packet format for ARM:
......@@ -398,7 +398,7 @@ int armv7m_run_algorithm(struct target_s *target,
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
// uint32_t regvalue;
if (!reg)
......@@ -462,7 +462,7 @@ int armv7m_run_algorithm(struct target_s *target,
{
if (reg_params[i].direction != PARAM_OUT)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
......@@ -530,7 +530,7 @@ struct reg_cache *armv7m_build_reg_cache(target_t *target)
int num_regs = ARMV7M_NUM_REGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
......
......@@ -140,7 +140,7 @@ int armv7m_mode_to_number(enum armv7m_mode mode);
int armv7m_arch_state(struct target_s *target);
int armv7m_get_gdb_reg_list(target_t *target,
reg_t **reg_list[], int *reg_list_size);
struct reg **reg_list[], int *reg_list_size);
int armv7m_register_commands(struct command_context_s *cmd_ctx);
int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m);
......
......@@ -53,7 +53,7 @@ static int cortex_m3_store_core_reg_u32(target_t *target,
#ifdef ARMV7_GDB_HACKS
extern uint8_t armv7m_gdb_dummy_cpsr_value[];
extern reg_t armv7m_gdb_dummy_cpsr_reg;
extern struct reg armv7m_gdb_dummy_cpsr_reg;
#endif
static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
......@@ -1453,14 +1453,14 @@ struct dwt_reg_state {
uint32_t value; /* scratch/cache */
};
static int cortex_m3_dwt_get_reg(struct reg_s *reg)
static int cortex_m3_dwt_get_reg(struct reg *reg)
{
struct dwt_reg_state *state = reg->arch_info;
return target_read_u32(state->target, state->addr, &state->value);
}
static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf)
static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
{
struct dwt_reg_state *state = reg->arch_info;
......@@ -1495,7 +1495,7 @@ static struct dwt_reg dwt_comp[] = {
static int dwt_reg_type = -1;
static void
cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
cortex_m3_dwt_addreg(struct target_s *t, struct reg *r, struct dwt_reg *d)
{
struct dwt_reg_state *state;
......
......@@ -146,7 +146,7 @@ static const struct {
static int embeddedice_reg_arch_type = -1;
static int embeddedice_get_reg(reg_t *reg)
static int embeddedice_get_reg(struct reg *reg)
{
int retval;
......@@ -168,7 +168,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = NULL;
struct reg *reg_list = NULL;
struct embeddedice_reg *arch_info = NULL;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
......@@ -185,7 +185,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
num_regs--;
/* the actual registers are kept in two arrays */
reg_list = calloc(num_regs, sizeof(reg_t));
reg_list = calloc(num_regs, sizeof(struct reg));
arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
/* fill in values for the reg cache */
......@@ -312,7 +312,7 @@ int embeddedice_setup(target_t *target)
*/
if (arm7_9->has_monitor_mode)
{
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
......@@ -328,7 +328,7 @@ int embeddedice_setup(target_t *target)
* optionally checking the value read.
* Note that at this level, all registers are 32 bits wide.
*/
int embeddedice_read_reg_w_check(reg_t *reg,
int embeddedice_read_reg_w_check(struct reg *reg,
uint8_t *check_value, uint8_t *check_mask)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
......@@ -449,7 +449,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
* Queue a read for an EmbeddedICE register into the register cache,
* not checking the value read.
*/
int embeddedice_read_reg(reg_t *reg)
int embeddedice_read_reg(struct reg *reg)
{
return embeddedice_read_reg_w_check(reg, NULL, NULL);
}
......@@ -458,7 +458,7 @@ int embeddedice_read_reg(reg_t *reg)
* Queue a write for an EmbeddedICE register, updating the register cache.