Commit ccc2e3fe authored by oharboe's avatar oharboe
Browse files

Laurentiu Cocanu - memory read/write and exit() error path fixes

git-svn-id: svn://svn.berlios.de/openocd/trunk@1064 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent af41e6aa
......@@ -983,6 +983,7 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
int retval;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 dst_min_alignment, wcount, bytes_remaining = count;
......@@ -1033,7 +1034,10 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
{
return retval;
}
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
......
This diff is collapsed.
......@@ -241,6 +241,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
*/
int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
{
int retval;
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
mem_param_t mem_params[2];
......@@ -263,7 +264,10 @@ int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 resul
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate);
if((retval = target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
{
return retval;
}
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
......
......@@ -204,10 +204,10 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
{
/* register flash specific commands */
if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
LOG_ERROR("couldn't register '%s' commands", args[0]);
exit(-1);
return retval;
}
c = malloc(sizeof(nand_device_t));
......
......@@ -410,7 +410,7 @@ int ft2232_send_and_recv(jtag_command_t *first, jtag_command_t *last)
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
exit(-1);
return retval;
}
#ifdef _DEBUG_USB_IO_
......@@ -429,7 +429,7 @@ int ft2232_send_and_recv(jtag_command_t *first, jtag_command_t *last)
if ((retval = ft2232_read(ft2232_buffer, ft2232_expect_read, &bytes_read)) != ERROR_OK)
{
LOG_ERROR("couldn't read from FT2232");
exit(-1);
return retval;
}
#ifdef _DEBUG_USB_IO_
......
......@@ -1720,6 +1720,7 @@ static int default_speed_div(int speed, int *khz)
int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int i;
int retval;
/* check whether the interface is already configured */
if (jtag_interface)
......@@ -1738,8 +1739,10 @@ int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char
{
if (strcmp(args[0], jtag_interfaces[i]->name) == 0)
{
if (jtag_interfaces[i]->register_commands(cmd_ctx) != ERROR_OK)
exit(-1);
if ((retval = jtag_interfaces[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
return retval;
}
jtag_interface = jtag_interfaces[i];
......
......@@ -217,14 +217,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
{
return retval;
}
target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
{
return retval;
}
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
......@@ -235,14 +241,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
{
return retval;
}
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
......@@ -291,17 +303,29 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
{
return retval;
}
if (current_instr==arm7_9->arm_bkpt)
target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
{
return retval;
}
if (current_instr==arm7_9->thumb_bkpt)
target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 0;
}
......@@ -2306,6 +2330,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int i;
......@@ -2332,7 +2357,10 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
}
/* write DCC code to working area */
target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
{
return retval;
}
}
armv4_5_algorithm_t armv4_5_info;
......@@ -2348,7 +2376,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
int retval;
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
......
......@@ -233,6 +233,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
......@@ -294,10 +295,10 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm7_9_execute_sys_speed(target);
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("failed executing JTAG queue, exiting");
exit(-1);
return retval;
}
return ERROR_OK;
......
......@@ -810,6 +810,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target)
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
int fp_num=0;
u32 hilo;
......@@ -851,8 +852,14 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u8 code[4];
buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr);
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code);
if((retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
{
return retval;
}
breakpoint->set = 0x11; /* Any nice value but 0 */
}
......@@ -861,6 +868,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
......@@ -889,11 +897,17 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
}
breakpoint->set = 0;
......
......@@ -222,15 +222,17 @@ int embeddedice_setup(target_t *target)
int embeddedice_get_reg(reg_t *reg)
{
if (embeddedice_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
......@@ -381,12 +383,13 @@ void embeddedice_set_reg(reg_t *reg, u32 value)
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}
......
......@@ -160,15 +160,17 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
int etb_get_reg(reg_t *reg)
{
if (etb_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
......@@ -311,10 +313,11 @@ int etb_read_reg(reg_t *reg)
int etb_set_reg(reg_t *reg, u32 value)
{
if (etb_write_reg(reg, value) != ERROR_OK)
int retval;
if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
......@@ -326,12 +329,13 @@ int etb_set_reg(reg_t *reg, u32 value)
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}
......
......@@ -311,15 +311,17 @@ int etm_setup(target_t *target)
int etm_get_reg(reg_t *reg)
{
if (etm_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = etm_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
......@@ -389,10 +391,11 @@ int etm_read_reg(reg_t *reg)
int etm_set_reg(reg_t *reg, u32 value)
{
if (etm_write_reg(reg, value) != ERROR_OK)
int retval;
if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
......@@ -404,12 +407,13 @@ int etm_set_reg(reg_t *reg, u32 value)
int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}
......
......@@ -523,6 +523,7 @@ int feroceon_examine_debug_reason(target_t *target)
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
......@@ -579,7 +580,10 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK)
{
return retval;
}
}
/* backup clobbered processor state */
......
......@@ -533,10 +533,10 @@ int target_init(struct command_context_s *cmd_ctx)
target->type->examine = default_examine;
}
if (target->type->init_target(cmd_ctx, target) != ERROR_OK)
if ((retval = target->type->init_target(cmd_ctx, target)) != ERROR_OK)
{
LOG_ERROR("target '%s' init failed", target->type->name);
exit(-1);
return retval;
}
/* Set up default functions if none are provided by target */
......
......@@ -2142,6 +2142,7 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca
int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
......@@ -2186,16 +2187,28 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->length == 4)
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
{
return retval;
}
}
else
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 1;
}
......@@ -2242,6 +2255,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
......@@ -2276,11 +2290,17 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 0;
}
......
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