Commit cb434c21 authored by oharboe's avatar oharboe
Browse files

error checking - no reported errors, but catched a couple of exit()'s and converted them to errors.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1175 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 6c15861b
......@@ -143,13 +143,13 @@ flash_errmsg(int err)
int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
ecosflash_flash_bank_t *info;
if (argc < 7)
{
LOG_WARNING("incomplete flash_bank ecosflash configuration");
return ERROR_FLASH_BANK_INVALID;
}
info = malloc(sizeof(ecosflash_flash_bank_t));
if(info == NULL)
{
......@@ -159,7 +159,7 @@ int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
bank->driver_priv = info;
info->driverPath=strdup(args[6]);
/* eCos flash sector sizes are not exposed to OpenOCD, use 0x10000 as
/* eCos flash sector sizes are not exposed to OpenOCD, use 0x10000 as
* a way to improve impeadance matach between OpenOCD and eCos flash
* driver.
*/
......@@ -175,12 +175,12 @@ int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, c
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 0;
}
info->target = get_target_by_num(strtoul(args[5], NULL, 0));
if (info->target == NULL)
{
LOG_ERROR("no target '%i' configured", (int)strtoul(args[5], NULL, 0));
exit(-1);
return ERROR_FAIL;
}
return ERROR_OK;
}
......@@ -190,20 +190,20 @@ int loadDriver(ecosflash_flash_bank_t *info)
{
u32 buf_cnt;
u32 image_size;
image_t image;
image_t image;
image.base_address_set = 0;
image.start_address_set = 0;
target_t *target=info->target;
int retval;
if ((retval=image_open(&image, info->driverPath, NULL)) != ERROR_OK)
{
return retval;
}
info->start_address=image.start_address;
image_size = 0x0;
int i;
for (i = 0; i < image.num_sections; i++)
......@@ -219,7 +219,7 @@ int loadDriver(ecosflash_flash_bank_t *info)
target_write_buffer(target, image.sections[i].base_address, buf_cnt, buffer);
image_size += buf_cnt;
LOG_DEBUG("%u byte written at address 0x%8.8x", buf_cnt, image.sections[i].base_address);
free(buffer);
}
......@@ -237,8 +237,8 @@ static int const OFFSET_GET_WORKAREA=0x18;
static int const OFFSET_GET_WORKAREA_SIZE=0x4;
int runCode(ecosflash_flash_bank_t *info,
u32 codeStart, u32 codeStop, u32 r0, u32 r1, u32 r2,
int runCode(ecosflash_flash_bank_t *info,
u32 codeStart, u32 codeStop, u32 r0, u32 r1, u32 r2,
u32 *result,
/* timeout in ms */
int timeout)
......@@ -250,45 +250,45 @@ int runCode(ecosflash_flash_bank_t *info,
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, r0);
buf_set_u32(reg_params[1].value, 0, 32, r1);
buf_set_u32(reg_params[2].value, 0, 32, r2);
int retval;
if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
codeStart,
codeStop, timeout,
codeStop, timeout,
&armv4_5_info)) != ERROR_OK)
{
LOG_ERROR("error executing eCos flash algorithm");
return retval;
}
*result=buf_get_u32(reg_params[0].value, 0, 32);
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]);
return ERROR_OK;
}
int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
{
int retval;
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
retval=loadDriver(info);
if (retval!=ERROR_OK)
return retval;
u32 flashErr;
retval=runCode(info,
retval=runCode(info,
info->start_address+OFFSET_ERASE,
info->start_address+OFFSET_ERASE+OFFSET_ERASE_SIZE,
address,
......@@ -299,7 +299,7 @@ int eCosBoard_erase(ecosflash_flash_bank_t *info, u32 address, u32 len)
);
if (retval!=ERROR_OK)
return retval;
if (flashErr != 0x0)
{
LOG_ERROR("Flash erase failed with %d (%s)\n", flashErr, flash_errmsg(flashErr));
......@@ -315,13 +315,13 @@ int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 l
const int chunk=8192;
int retval=ERROR_OK;
int timeout = (chunk / 20480 + 1) * 1000; /*asume 20 KB/s + 1 second*/
retval=loadDriver(info);
if (retval!=ERROR_OK)
return retval;
u32 buffer;
retval=runCode(info,
retval=runCode(info,
info->start_address+OFFSET_GET_WORKAREA,
info->start_address+OFFSET_GET_WORKAREA+OFFSET_GET_WORKAREA_SIZE,
0,
......@@ -331,8 +331,8 @@ int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 l
1000);
if (retval!=ERROR_OK)
return retval;
int i;
for (i=0; i<len; i+=chunk)
{
......@@ -341,14 +341,14 @@ int eCosBoard_flash(ecosflash_flash_bank_t *info, void *data, u32 address, u32 l
{
t=chunk;
}
int retval;
retval=target_write_buffer(target, buffer, t, ((u8 *)data)+i);
if (retval != ERROR_OK)
return retval;
u32 flashErr;
retval=runCode(info,
retval=runCode(info,
info->start_address+OFFSET_FLASH,
info->start_address+OFFSET_FLASH+OFFSET_FLASH_SIZE,
buffer,
......@@ -378,7 +378,7 @@ int ecosflash_probe(struct flash_bank_s *bank)
int ecosflash_register_commands(struct command_context_s *cmd_ctx)
{
register_command(cmd_ctx, NULL, "ecosflash", NULL, COMMAND_ANY, NULL);
return ERROR_OK;
}
......@@ -387,7 +387,7 @@ static void command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
{
ecosflash_flash_bank_t *info = bank->driver_priv;
int i;
if (info->target->endianness == TARGET_LITTLE_ENDIAN)
{
for (i = bank->bus_width; i > 0; i--)
......@@ -417,16 +417,16 @@ u32 ecosflash_address(struct flash_bank_s *bank, u32 address)
case 1:
retval = address;
}
return retval + bank->base;
}
}
int ecosflash_erase(struct flash_bank_s *bank, int first, int last)
{
struct flash_bank_s *c=bank;
ecosflash_flash_bank_t *info = bank->driver_priv;
return eCosBoard_erase(info, c->base+first*sectorSize, sectorSize*(last-first+1));
return eCosBoard_erase(info, c->base+first*sectorSize, sectorSize*(last-first+1));
}
int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last)
......@@ -463,7 +463,7 @@ u32 ecosflash_get_flash_status(flash_bank_t *bank)
void ecosflash_set_flash_mode(flash_bank_t *bank,int mode)
{
}
u32 ecosflash_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
......
......@@ -63,11 +63,11 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
int etb_set_instr(etb_t *etb, u32 new_instr)
{
jtag_device_t *device = jtag_get_device(etb->chain_pos);
if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
{
scan_field_t field;
field.device = etb->chain_pos;
field.num_bits = device->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
......@@ -78,12 +78,12 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
}
return ERROR_OK;
}
......@@ -92,7 +92,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
if(etb->cur_scan_chain != new_scan_chain)
{
scan_field_t field;
field.device = etb->chain_pos;
field.num_bits = 5;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
......@@ -103,13 +103,13 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, -1);
etb->cur_scan_chain = new_scan_chain;
free(field.out_value);
}
......@@ -123,21 +123,21 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
etb_reg_t *arch_info = NULL;
int num_regs = 9;
int i;
/* register a register arch-type for etm registers only once */
if (etb_reg_arch_type == -1)
etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
/* the actual registers are kept in two arrays */
reg_list = calloc(num_regs, sizeof(reg_t));
arch_info = calloc(num_regs, sizeof(etb_reg_t));
/* fill in values for the reg cache */
reg_cache->name = "etb registers";
reg_cache->next = NULL;
reg_cache->reg_list = reg_list;
reg_cache->num_regs = num_regs;
/* set up registers */
for (i = 0; i < num_regs; i++)
{
......@@ -154,7 +154,7 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
arch_info[i].addr = i;
arch_info[i].etb = etb;
}
return reg_cache;
}
......@@ -166,13 +166,13 @@ int etb_get_reg(reg_t *reg)
LOG_ERROR("BUG: error scheduling etm register read");
return retval;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
}
......@@ -180,11 +180,11 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
{
scan_field_t fields[3];
int i;
jtag_add_end_state(TAP_RTI);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
fields[0].device = etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
......@@ -194,7 +194,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
......@@ -216,31 +216,31 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler = buf_to_u32_handler;
for (i = 0; i < num_frames; i++)
{
/* ensure nR/W reamins set to read */
buf_set_u32(fields[2].out_value, 0, 1, 0);
/* address remains set to 0x4 (RAM data) until we read the last frame */
if (i < num_frames - 1)
buf_set_u32(fields[1].out_value, 0, 7, 4);
else
buf_set_u32(fields[1].out_value, 0, 7, 0);
fields[0].in_handler_priv = &data[i];
jtag_add_dr_scan(3, fields, -1);
}
jtag_execute_queue();
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
......@@ -249,13 +249,13 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
etb_reg_t *etb_reg = reg->arch_info;
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i", etb_reg->addr);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].device = etb_reg->etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
......@@ -265,7 +265,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb_reg->etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
......@@ -287,28 +287,28 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
*/
buf_set_u32(fields[1].out_value, 0, 7, 0x0);
fields[0].in_value = reg->value;
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
int etb_read_reg(reg_t *reg)
{
return etb_read_reg_w_check(reg, NULL, NULL);
return etb_read_reg_w_check(reg, NULL, NULL);
}
int etb_set_reg(reg_t *reg, u32 value)
......@@ -319,11 +319,11 @@ int etb_set_reg(reg_t *reg, u32 value)
LOG_ERROR("BUG: error scheduling etm register write");
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->dirty = 0;
return ERROR_OK;
}
......@@ -331,7 +331,7 @@ int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
......@@ -345,13 +345,13 @@ int etb_write_reg(reg_t *reg, u32 value)
etb_reg_t *etb_reg = reg->arch_info;
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].device = etb_reg->etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
......@@ -362,7 +362,7 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb_reg->etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
......@@ -384,13 +384,13 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
free(fields[0].out_value);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
......@@ -402,9 +402,9 @@ int etb_store_reg(reg_t *reg)
int etb_register_commands(struct command_context_s *cmd_ctx)
{
command_t *etb_cmd;
etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
return ERROR_OK;
......@@ -416,41 +416,40 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
jtag_device_t *jtag_device;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
if (argc != 2)
{
LOG_ERROR("incomplete 'etb config <target> <chain_pos>' command");
exit(-1);
return ERROR_COMMAND_SYNTAX_ERROR;
}
target = get_target_by_num(strtoul(args[0], NULL, 0));
if (!target)
{
LOG_ERROR("target number '%s' not defined", args[0]);
exit(-1);
return ERROR_FAIL;
}
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
return ERROR_OK;
return ERROR_FAIL;
}
jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
if (!jtag_device)
{
LOG_ERROR("jtag device number '%s' not defined", args[1]);
exit(-1);
return ERROR_FAIL;
}
if (arm7_9->etm_ctx)
{
etb_t *etb = malloc(sizeof(etb_t));
arm7_9->etm_ctx->capture_driver_priv = etb;
etb->chain_pos = strtoul(args[1], NULL, 0);
etb->cur_scan_chain = -1;
etb->reg_cache = NULL;
......@@ -460,6 +459,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
else
{
LOG_ERROR("target has no ETM defined, ETB left unconfigured");
return ERROR_FAIL;
}
return ERROR_OK;
......@@ -468,9 +468,9 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
int etb_init(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
etb->etm_ctx = etm_ctx;
/* identify ETB RAM depth and width */
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
......@@ -478,16 +478,16 @@ int etb_init(etm_context_t *etm_ctx)
etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
return ERROR_OK;
}
trace_status_t etb_status(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
etb->etm_ctx = etm_ctx;
/* if tracing is currently idle, return this information */
if (etm_ctx->capture_status == TRACE_IDLE)
{
......@@ -497,10 +497,10 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
{
reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
int etb_timeout = 100;
/* trace is running, check the ETB status flags */
etb_get_reg(etb_status_reg);
/* check Full bit to identify an overflow */
if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
etm_ctx->capture_status |= TRACE_OVERFLOWED;
......@@ -517,23 +517,23 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
/* wait for data formatter idle */