Commit c45de807 authored by kc8apf's avatar kc8apf
Browse files

Change tap_state naming to be consistent with SVF documentation.

Courtesy of Dick Hollenbeck <dick@softplc.com>


git-svn-id: svn://svn.berlios.de/openocd/trunk@1232 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 6c27550f
......@@ -145,7 +145,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
scan_field_t field;
u8 status;
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR;
field.tap = tap;
......@@ -158,7 +158,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
LOG_DEBUG("status: 0x%2.2x", status);
......@@ -181,7 +181,7 @@ int str9xpec_isc_enable(struct flash_bank_s *bank)
return ERROR_OK;
/* enter isc mode */
if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* check ISC status */
......@@ -207,7 +207,7 @@ int str9xpec_isc_disable(struct flash_bank_s *bank)
if (!str9xpec_info->isc_enable)
return ERROR_OK;
if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* delay to handle aborts */
......@@ -238,7 +238,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */
str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI);
str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -250,7 +250,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
......@@ -349,10 +349,10 @@ int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
armv4_5 = bank->target->arch_info;
arm7_9 = armv4_5->arch_info;
jtag_info = &arm7_9->jtag_info;
str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
str9xpec_info->isc_enable = 0;
str9xpec_build_block_list(bank);
/* clear option byte register */
......@@ -390,7 +390,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
}
/* execute ISC_BLANK_CHECK command */
str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI);
str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -402,7 +402,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_add_sleep(40000);
/* read blank check result */
......@@ -416,7 +416,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_add_dr_scan(1, &field, TAP_IRPAUSE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
......@@ -506,7 +506,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */
str9xpec_set_instr(tap, ISC_ERASE, TAP_PI);
str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -518,7 +518,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
jtag_add_sleep(10);
......@@ -569,9 +569,9 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI);
str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_IDLE);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
......@@ -658,7 +658,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
tap = str9xpec_info->tap;
/* set flash controller address */
str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI);
str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 8;
......@@ -747,7 +747,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (dwords_remaining > 0)
{
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -759,12 +759,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
......@@ -807,7 +807,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
bytes_written++;
}
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -819,12 +819,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
......@@ -889,7 +889,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
buffer = calloc(CEIL(32, 8), 1);
str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI);
str9xpec_set_instr(tap, ISC_IDCODE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 32;
......@@ -901,7 +901,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32);
......@@ -1014,7 +1014,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
......@@ -1026,12 +1026,12 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
......@@ -1303,13 +1303,13 @@ int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx
}
/* enable turbo mode - TURBO-PROG-ENABLE */
str9xpec_set_instr(tap2, 0xD, TAP_RTI);
str9xpec_set_instr(tap2, 0xD, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
/* modify scan chain - str9 core has been removed */
tap1->enabled = 0;
return ERROR_OK;
}
......@@ -1337,11 +1337,11 @@ int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ct
if (tap == NULL)
return ERROR_FAIL;
/* exit turbo mode via TLR */
str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR);
str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
jtag_execute_queue();
/* restore previous scan chain */
if (tap->next_tap) {
tap->next_tap->enabled = 1;
......
......@@ -109,13 +109,13 @@ u8 amt_jtagaccel_tap_move[6][6][2] =
{{0x1f, 0x00}, {0x0c, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x08, 0x00}, {0x00, 0x00}}, /* PI */
};
jtag_interface_t amt_jtagaccel_interface =
jtag_interface_t amt_jtagaccel_interface =
{
.name = "amt_jtagaccel",
.execute_queue = amt_jtagaccel_execute_queue,
.speed = amt_jtagaccel_speed,
.speed = amt_jtagaccel_speed,
.register_commands = amt_jtagaccel_register_commands,
.init = amt_jtagaccel_init,
.quit = amt_jtagaccel_quit,
......@@ -127,7 +127,7 @@ int amt_jtagaccel_register_commands(struct command_context_s *cmd_ctx)
COMMAND_CONFIG, NULL);
register_command(cmd_ctx, NULL, "rtck", amt_jtagaccel_handle_rtck_command,
COMMAND_CONFIG, NULL);
return ERROR_OK;
}
......@@ -142,7 +142,7 @@ void amt_jtagaccel_reset(int trst, int srst)
aw_control_rst |= 0x1;
else if (srst == 0)
aw_control_rst &= ~0x1;
AMT_AW(aw_control_rst);
}
......@@ -151,7 +151,7 @@ int amt_jtagaccel_speed(int speed)
aw_control_baudrate &= 0xf0;
aw_control_baudrate |= speed & 0x0f;
AMT_AW(aw_control_baudrate);
return ERROR_OK;
}
......@@ -170,11 +170,11 @@ void amt_wait_scan_busy(void)
{
int timeout = 4096;
u8 ar_status;
AMT_AR(ar_status);
while (((ar_status) & 0x80) && (timeout-- > 0))
AMT_AR(ar_status);
if (ar_status & 0x80)
{
LOG_ERROR("amt_jtagaccel timed out while waiting for end of scan, rtck was %s, last AR_STATUS: 0x%2.2x", (rtck_enabled) ? "enabled" : "disabled", ar_status);
......@@ -186,15 +186,15 @@ void amt_jtagaccel_state_move(void)
{
u8 aw_scan_tms_5;
u8 tms_scan[2];
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
aw_scan_tms_5 = 0x40 | (tms_scan[0] & 0x1f);
AMT_AW(aw_scan_tms_5);
if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy();
if (tms_scan[0] & 0x80)
{
aw_scan_tms_5 = 0x40 | (tms_scan[1] & 0x1f);
......@@ -202,7 +202,7 @@ void amt_jtagaccel_state_move(void)
if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy();
}
cur_state = end_state;
}
......@@ -213,27 +213,27 @@ void amt_jtagaccel_runtest(int num_cycles)
u8 aw_scan_tms_1to4;
enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
amt_jtagaccel_end_state(TAP_RTI);
amt_jtagaccel_end_state(TAP_IDLE);
amt_jtagaccel_state_move();
}
while (num_cycles - i >= 5)
{
aw_scan_tms_5 = 0x40;
AMT_AW(aw_scan_tms_5);
i += 5;
}
if (num_cycles - i > 0)
{
aw_scan_tms_1to4 = 0x80 | ((num_cycles - i - 1) & 0x3) << 4;
AMT_AW(aw_scan_tms_1to4);
}
amt_jtagaccel_end_state(saved_end_state);
if (cur_state != end_state)
amt_jtagaccel_state_move();
......@@ -251,9 +251,9 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
u8 tms_scan[2];
if (ir_scan)
amt_jtagaccel_end_state(TAP_SI);
amt_jtagaccel_end_state(TAP_IRSHIFT);
else
amt_jtagaccel_end_state(TAP_SD);
amt_jtagaccel_end_state(TAP_DRSHIFT);
amt_jtagaccel_state_move();
amt_jtagaccel_end_state(saved_end_state);
......@@ -263,7 +263,7 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
{
aw_tdi_option = 0x30 | (((scan_size - 1) % 8) - 1);
AMT_AW(aw_tdi_option);
dw_tdi_scan = buf_get_u32(buffer, bit_count, (scan_size - 1) % 8) & 0xff;
AMT_DW(dw_tdi_scan);
if (jtag_speed > 3 || rtck_enabled)
......@@ -275,11 +275,11 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
dr_tdo = dr_tdo >> (8 - ((scan_size - 1) % 8));
buf_set_u32(buffer, bit_count, (scan_size - 1) % 8, dr_tdo);
}
bit_count += (scan_size - 1) % 8;
bits_left -= (scan_size - 1) % 8;
}
while (bits_left - 1 >= 8)
{
dw_tdi_scan = buf_get_u32(buffer, bit_count, 8) & 0xff;
......@@ -292,11 +292,11 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
AMT_DR(dr_tdo);
buf_set_u32(buffer, bit_count, 8, dr_tdo);
}
bit_count += 8;
bits_left -= 8;
}
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
aw_tms_scan = 0x40 | (tms_scan[0] & 0x1f) | (buf_get_u32(buffer, bit_count, 1) << 5);
......@@ -310,7 +310,7 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
dr_tdo = dr_tdo >> 7;
buf_set_u32(buffer, bit_count, 1, dr_tdo);
}
if (tms_scan[0] & 0x80)
{
aw_tms_scan = 0x40 | (tms_scan[1] & 0x1f);
......@@ -328,12 +328,12 @@ int amt_jtagaccel_execute_queue(void)
enum scan_type type;
u8 *buffer;
int retval;
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler
*/
*/
retval = ERROR_OK;
while (cmd)
{
switch (cmd->type)
......@@ -351,7 +351,7 @@ int amt_jtagaccel_execute_queue(void)
#endif
if (cmd->cmd.reset->trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
amt_jtagaccel_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
......@@ -397,7 +397,7 @@ int amt_jtagaccel_execute_queue(void)
}
cmd = cmd->next;
}
return retval;
}
......@@ -409,16 +409,16 @@ int amt_jtagaccel_get_giveio_access(void)
version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) {
errno = EINVAL;
return -1;
errno = EINVAL;
return -1;
}
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
return 0;
return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) {
errno = ENODEV;
return -1;
errno = ENODEV;
return -1;
}
CloseHandle( h );
......@@ -437,7 +437,7 @@ int amt_jtagaccel_init(void)
u8 status_port;
#endif
u8 ar_status;
#if PARPORT_USE_PPDEV == 1
if (device_handle > 0)
{
......@@ -447,7 +447,7 @@ int amt_jtagaccel_init(void)
snprintf(buffer, 256, "/dev/parport%d", amt_jtagaccel_port);
device_handle = open(buffer, O_RDWR);
if (device_handle < 0)
{
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
......@@ -468,7 +468,7 @@ int amt_jtagaccel_init(void)
LOG_ERROR(" cannot set compatible mode to device");
return ERROR_JTAG_INIT_FAILED;
}
control_port = 0x00;
i = ioctl(device_handle, PPWCONTROL, &control_port);
......@@ -484,57 +484,57 @@ int amt_jtagaccel_init(void)
#if PARPORT_USE_GIVEIO == 1
if (amt_jtagaccel_get_giveio_access() != 0) {
#else /* PARPORT_USE_GIVEIO */
#else /* PARPORT_USE_GIVEIO */
if (ioperm(amt_jtagaccel_port, 5, 1) != 0) {
#endif /* PARPORT_USE_GIVEIO */
LOG_ERROR("missing privileges for direct i/o");
return ERROR_JTAG_INIT_FAILED;
}
/* prepare epp port */
/* clear timeout */
status_port = inb(amt_jtagaccel_port + 1);
outb(status_port | 0x1, amt_jtagaccel_port + 1);
/* reset epp port */
outb(0x00, amt_jtagaccel_port + 2);
outb(0x04, amt_jtagaccel_port + 2);
#endif
if (rtck_enabled)
{
{
/* set RTCK enable bit */
aw_control_fsm |= 0x02;
}
/* enable JTAG port */
aw_control_fsm |= 0x04;
AMT_AW(aw_control_fsm);
amt_jtagaccel_speed(jtag_speed);
if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
aw_control_rst &= ~0x8;
else
aw_control_rst |= 0x8;
if (jtag_reset_config & RESET_SRST_PUSH_PULL)
aw_control_rst &= ~0x2;
else
aw_control_rst |= 0x2;
amt_jtagaccel_reset(0, 0);
/* read status register */
AMT_AR(ar_status);
LOG_DEBUG("AR_STATUS: 0x%2.2x", ar_status);
return ERROR_OK;
}
int amt_jtagaccel_quit(void)
{
return ERROR_OK;
}
......@@ -568,6 +568,6 @@ int amt_jtagaccel_handle_rtck_command(struct command_context_s *cmd_ctx, char *c
rtck_enabled = 0;
}
}
return ERROR_OK;
}
......@@ -41,24 +41,24 @@ bitbang_interface_t *bitbang_interface;
/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
*
*
* Set this to 1 and str912 reset halt will fail.
*
*
* If someone can submit a patch with an explanation it will be greatly
* appreciated, but as far as I can tell (ØH) DCLK is generated upon
* clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI
* clk=0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
* state". With hardware there is no such thing as *while* in a state. There
* are only edges. So clk => 0 is in fact a very subtle state transition that
* happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
*
* happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
*
* For "reset halt" the last thing that happens before srst is asserted
* is that the breakpoint is set up. If DCLK is not wiggled one last
* time before the reset, then the breakpoint is not set up and
* "reset halt" will fail to halt.
*
*
*/
#define CLOCK_IDLE() 0
#define CLOCK_IDLE() 0
int bitbang_execute_queue(void);
......@@ -76,10 +76,10 @@ void bitbang_end_state(enum tap_state state)
}
void bitbang_state_move(void) {
int i=0, tms=0;
u8 tms_scan = TAP_MOVE(cur_state, end_state);
for (i = 0; i < 7; i++)
{
tms = (tms_scan >> i) & 1;
......@@ -87,7 +87,7 @@ void bitbang_state_move(void) {
bitbang_interface->write(1, tms, 0);
}
bitbang_interface->write(CLOCK_IDLE(), tms, 0);
cur_state = end_state;
}
......@@ -113,7 +113,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
exit(-1);
}
bitbang_interface->write(0, tms, 0);
bitbang_interface->write(1, tms, 0);
......@@ -121,7 +121,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
state_count++;
num_states--;
}