Commit c3b90c05 authored by Tim Newsome's avatar Tim Newsome Committed by Matthias Welwarsky
Browse files

flash/nor: use target_addr_t for flash bank base



This should allow users to configure flash at >32-bit addresses.

Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c
Signed-off-by: default avatarTim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4919


Tested-by: jenkins
Reviewed-by: default avatarTomas Vanek <vanekt@fbl.cz>
parent 57e30102
......@@ -833,8 +833,8 @@ static int stm32x_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
} else {
LOG_WARNING("STM32H flash bank base address config is incorrect."
" 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
LOG_WARNING("STM32H flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
......
......@@ -816,8 +816,9 @@ static int stm32lx_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
} else {
LOG_WARNING("STM32L flash bank base address config is incorrect."
" 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
LOG_WARNING("STM32L flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
" or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
......
......@@ -559,13 +559,13 @@ static int stmsmi_probe(struct flash_bank *bank)
stmsmi_info->bank_num = SMI_SEL_BANK3;
break;
default:
LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
io_base = target_device->io_base;
stmsmi_info->io_base = io_base;
LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
/* read and decode flash ID; returns in SW mode */
......
......@@ -112,7 +112,7 @@ COMMAND_HANDLER(handle_flash_info_command)
LOG_WARNING("Flash protection check is not implemented.");
command_print(CMD_CTX,
"#%d : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32
"#%d : %s at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32
", buswidth %i, chipwidth %i",
p->bank_number,
p->driver->name,
......@@ -177,7 +177,7 @@ COMMAND_HANDLER(handle_flash_probe_command)
retval = p->driver->probe(p);
if (retval == ERROR_OK)
command_print(CMD_CTX,
"flash '%s' found at 0x%8.8" PRIx32,
"flash '%s' found at " TARGET_ADDR_FMT,
p->driver->name,
p->base);
} else {
......@@ -205,7 +205,8 @@ COMMAND_HANDLER(handle_flash_erase_check_command)
command_print(CMD_CTX, "successfully checked erase state");
else {
command_print(CMD_CTX,
"unknown error when checking erase state of flash bank #%s at 0x%8.8" PRIx32,
"unknown error when checking erase state of flash bank #%s at "
TARGET_ADDR_FMT,
CMD_ARGV[0],
p->base);
}
......@@ -239,7 +240,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
{
struct flash_bank *p;
int retval = ERROR_OK;
uint32_t address;
target_addr_t address;
uint32_t length;
bool do_pad = false;
bool do_unlock = false;
......@@ -262,7 +263,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
if (length <= 0) {
......@@ -288,7 +289,8 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
retval = flash_erase_address_range(target, do_pad, address, length);
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")"
command_print(CMD_CTX, "erased address " TARGET_ADDR_FMT " (length %"
PRIi32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
......@@ -1138,7 +1140,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
c->name = strdup(bank_name);
c->target = target;
c->driver = driver;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[1], c->base);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
......@@ -1148,8 +1150,8 @@ COMMAND_HANDLER(handle_flash_bank_command)
int retval;
retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
if (ERROR_OK != retval) {
LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32 "; usage: %s",
driver_name, c->base, driver->usage);
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
"; usage: %s", driver_name, c->base, driver->usage);
free(c);
return retval;
}
......@@ -1169,7 +1171,7 @@ COMMAND_HANDLER(handle_flash_banks_command)
unsigned n = 0;
for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) {
LOG_USER("#%d : %s (%s) at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", "
LOG_USER("#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", "
"buswidth %u, chipwidth %u", p->bank_number,
p->name, p->driver->name, p->base, p->size,
p->bus_width, p->chip_width);
......
......@@ -165,7 +165,8 @@ static int tms470_read_part_info(struct flash_bank *bank)
part_name = "TMS470R1A256";
if (bank->base >= 0x00040000) {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address "
TARGET_ADDR_FMT ".",
part_name,
bank->base);
return ERROR_FLASH_OPERATION_FAILED;
......@@ -204,7 +205,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
sizeof(TMS470R1A288_BANK1_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
......@@ -244,7 +245,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
sizeof(TMS470R1A384_BANK2_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
......@@ -900,8 +901,8 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
tms470_read_part_info(bank);
LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" PRIx32 "", count, bank->base +
offset);
LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
count, bank->base + offset);
/* set GLBCTRL.4 */
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
......
......@@ -185,7 +185,7 @@ static int virtual_info(struct flash_bank *bank, char *buf, int buf_size)
if (master_bank == NULL)
return ERROR_FLASH_OPERATION_FAILED;
snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" PRIx32 "",
snprintf(buf, buf_size, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, master_bank->name, master_bank->base);
return ERROR_OK;
......
......@@ -305,7 +305,7 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
......
......@@ -778,7 +778,7 @@ static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
memcpy(&tmp_buf[start_pad], buffer, remaining);
if (end_pad) {
LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
bank->base + offset, end_pad);
memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
}
......
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