Commit c34e69cb authored by Aaron Carroll's avatar Aaron Carroll Committed by Øyvind Harboe
Browse files

cortex_a9: add source files for Cortex A9 support.



add target and build support for A9
Signed-off-by: default avatarAaron Carroll <aaronc@cse.unsw.edu.au>
parent 8e60d495
......@@ -73,7 +73,8 @@ ARMV7_SRC = \
armv7m.c \
cortex_m3.c \
armv7a.c \
cortex_a8.c
cortex_a8.c \
cortex_a9.c
ARM_DEBUG_SRC = \
arm_dpm.c \
......@@ -136,6 +137,7 @@ noinst_HEADERS = \
breakpoints.h \
cortex_m3.h \
cortex_a8.h \
cortex_a9.h \
embeddedice.h \
etb.h \
etm.h \
......
This diff is collapsed.
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2009 by Dirk Behme *
* dirk.behme@gmail.com - copy from cortex_m3 *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef CORTEX_A9_H
#define CORTEX_A9_H
#include "armv7a.h"
#define CORTEX_A9_COMMON_MAGIC 0x411fc082
#define CPUDBG_CPUID 0xD00
#define CPUDBG_CTYPR 0xD04
#define CPUDBG_TTYPR 0xD0C
#define CPUDBG_LOCKACCESS 0xFB0
#define CPUDBG_LOCKSTATUS 0xFB4
#define BRP_NORMAL 0
#define BRP_CONTEXT 1
#define CORTEX_A9_PADDRDBG_CPU_SHIFT 13
struct cortex_a9_brp
{
int used;
int type;
uint32_t value;
uint32_t control;
uint8_t BRPn;
};
struct cortex_a9_common
{
int common_magic;
struct arm_jtag jtag_info;
/* Context information */
uint32_t cpudbg_dscr;
/* Saved cp15 registers */
uint32_t cp15_control_reg;
/* Breakpoint register pairs */
int brp_num_context;
int brp_num;
int brp_num_available;
struct cortex_a9_brp *brp_list;
/* Use cortex_a9_read_regs_through_mem for fast register reads */
int fast_reg_read;
/* Flag that helps to resolve what ttb to use: user or kernel */
int current_address_mode;
struct armv7a_common armv7a_common;
};
static inline struct cortex_a9_common *
target_to_cortex_a9(struct target *target)
{
return container_of(target->arch_info, struct cortex_a9_common,
armv7a_common.armv4_5_common);
}
#endif /* CORTEX_A9_H */
......@@ -66,6 +66,7 @@ extern struct target_type dragonite_target;
extern struct target_type xscale_target;
extern struct target_type cortexm3_target;
extern struct target_type cortexa8_target;
extern struct target_type cortexa9_target;
extern struct target_type arm11_target;
extern struct target_type mips_m4k_target;
extern struct target_type avr_target;
......@@ -88,6 +89,7 @@ static struct target_type *target_types[] =
&xscale_target,
&cortexm3_target,
&cortexa8_target,
&cortexa9_target,
&arm11_target,
&mips_m4k_target,
&avr_target,
......
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