Commit c333611f authored by oharboe's avatar oharboe
Browse files

Update Embedded ICE registers explicitly during target->type->examine() instead

of as a side effect of target->type->poll(). This makes it clearer when things
happen during reset/examine.

git-svn-id: svn://svn.berlios.de/openocd/trunk@585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent c9dfba18
...@@ -84,27 +84,17 @@ int arm7_9_reinit_embeddedice(target_t *target) ...@@ -84,27 +84,17 @@ int arm7_9_reinit_embeddedice(target_t *target)
arm7_9_enable_sw_bkpts(target); arm7_9_enable_sw_bkpts(target);
} }
arm7_9->reinit_embeddedice = 0;
return ERROR_OK; return ERROR_OK;
} }
int arm7_9_jtag_callback(enum jtag_event event, void *priv) /* set things up after a reset / on startup */
int arm7_9_setup(target_t *target)
{ {
target_t *target = priv; /* a test-logic reset have occured
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* a test-logic reset occured
* the EmbeddedICE registers have been reset * the EmbeddedICE registers have been reset
* hardware breakpoints have been cleared * hardware breakpoints have been cleared
*/ */
if (event == JTAG_TRST_ASSERTED) return arm7_9_reinit_embeddedice(target);
{
arm7_9->reinit_embeddedice = 1;
}
return ERROR_OK;
} }
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
...@@ -686,11 +676,6 @@ int arm7_9_poll(target_t *target) ...@@ -686,11 +676,6 @@ int arm7_9_poll(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if (arm7_9->reinit_embeddedice)
{
arm7_9_reinit_embeddedice(target);
}
/* read debug status register */ /* read debug status register */
embeddedice_read_reg(dbg_stat); embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK) if ((retval = jtag_execute_queue()) != ERROR_OK)
...@@ -2635,8 +2620,6 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) ...@@ -2635,8 +2620,6 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
arm7_9->has_monitor_mode = 0; arm7_9->has_monitor_mode = 0;
arm7_9->has_vector_catch = 0; arm7_9->has_vector_catch = 0;
arm7_9->reinit_embeddedice = 0;
arm7_9->debug_entry_from_reset = 0; arm7_9->debug_entry_from_reset = 0;
arm7_9->dcc_working_area = NULL; arm7_9->dcc_working_area = NULL;
...@@ -2644,8 +2627,6 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) ...@@ -2644,8 +2627,6 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
arm7_9->fast_memory_access = 0; arm7_9->fast_memory_access = 0;
arm7_9->dcc_downloads = 0; arm7_9->dcc_downloads = 0;
jtag_register_event_callback(arm7_9_jtag_callback, target);
armv4_5->arch_info = arm7_9; armv4_5->arch_info = arm7_9;
armv4_5->read_core_reg = arm7_9_read_core_reg; armv4_5->read_core_reg = arm7_9_read_core_reg;
armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->write_core_reg = arm7_9_write_core_reg;
......
...@@ -53,7 +53,6 @@ typedef struct arm7_9_common_s ...@@ -53,7 +53,6 @@ typedef struct arm7_9_common_s
int has_monitor_mode; int has_monitor_mode;
int has_vector_catch; int has_vector_catch;
int reinit_embeddedice;
int debug_entry_from_reset; int debug_entry_from_reset;
struct working_area_s *dcc_working_area; struct working_area_s *dcc_working_area;
...@@ -105,6 +104,7 @@ int arm7_9_poll(target_t *target); ...@@ -105,6 +104,7 @@ int arm7_9_poll(target_t *target);
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer); int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
int arm7_9_setup(target_t *target);
int arm7_9_assert_reset(target_t *target); int arm7_9_assert_reset(target_t *target);
int arm7_9_deassert_reset(target_t *target); int arm7_9_deassert_reset(target_t *target);
int arm7_9_reset_request_halt(target_t *target); int arm7_9_reset_request_halt(target_t *target);
......
...@@ -769,6 +769,8 @@ int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) ...@@ -769,6 +769,8 @@ int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
} }
if ((retval=embeddedice_setup(target))!=ERROR_OK) if ((retval=embeddedice_setup(target))!=ERROR_OK)
return retval; return retval;
if ((retval=arm7_9_setup(target))!=ERROR_OK)
return retval;
if (arm7_9->etm_ctx) if (arm7_9->etm_ctx)
{ {
if ((retval=etm_setup(target))!=ERROR_OK) if ((retval=etm_setup(target))!=ERROR_OK)
......
...@@ -876,6 +876,8 @@ int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) ...@@ -876,6 +876,8 @@ int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
} }
if ((retval=embeddedice_setup(target))!=ERROR_OK) if ((retval=embeddedice_setup(target))!=ERROR_OK)
return retval; return retval;
if ((retval=arm7_9_setup(target))!=ERROR_OK)
return retval;
if (arm7_9->etm_ctx) if (arm7_9->etm_ctx)
{ {
if ((retval=etm_setup(target))!=ERROR_OK) if ((retval=etm_setup(target))!=ERROR_OK)
......
...@@ -201,6 +201,7 @@ extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask); ...@@ -201,6 +201,7 @@ extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
extern int etm_store_reg(reg_t *reg); extern int etm_store_reg(reg_t *reg);
extern int etm_set_reg(reg_t *reg, u32 value); extern int etm_set_reg(reg_t *reg, u32 value);
extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf); extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
extern int etm_setup(target_t *target);
int etm_register_commands(struct command_context_s *cmd_ctx); int etm_register_commands(struct command_context_s *cmd_ctx);
int etm_register_user_commands(struct command_context_s *cmd_ctx); int etm_register_user_commands(struct command_context_s *cmd_ctx);
......
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