Commit bcb0124b authored by oharboe's avatar oharboe
Browse files

dos2unix fix.

git-svn-id: svn://svn.berlios.de/openocd/trunk@339 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent e4821181
/*************************************************************************** /***************************************************************************
* Copyright (C) 2006 by Magnus Lundin * * Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu * * lundin@mlu.mine.nu *
* * * *
* This program is free software; you can redistribute it and/or modify * * This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by * * it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * * the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * * (at your option) any later version. *
* * * *
* This program is distributed in the hope that it will be useful, * * This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of * * but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * * GNU General Public License for more details. *
* * * *
* You should have received a copy of the GNU General Public License * * You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the * * along with this program; if not, write to the *
* Free Software Foundation, Inc., * * Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/ ***************************************************************************/
/*************************************************************************** /***************************************************************************
There are some things to notice There are some things to notice
* AT91SAM7S64 is tested * AT91SAM7S64 is tested
* All AT91SAM7Sxx and AT91SAM7Xxx should work but is not tested * All AT91SAM7Sxx and AT91SAM7Xxx should work but is not tested
* All parameters are identified from onchip configuartion registers * All parameters are identified from onchip configuartion registers
* *
* The flash controller handles erases automatically on a page (128/265 byte) basis * The flash controller handles erases automatically on a page (128/265 byte) basis
* Only an EraseAll command is supported by the controller * Only an EraseAll command is supported by the controller
* Partial erases can be implemented in software by writing one 0xFFFFFFFF word to * Partial erases can be implemented in software by writing one 0xFFFFFFFF word to
* some location in every page in the region to be erased * some location in every page in the region to be erased
* *
* Lock regions (sectors) are 32 or 64 pages * Lock regions (sectors) are 32 or 64 pages
* *
***************************************************************************/ ***************************************************************************/
#ifdef HAVE_CONFIG_H #ifdef HAVE_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#include "replacements.h" #include "replacements.h"
#include "at91sam7.h" #include "at91sam7.h"
#include "flash.h" #include "flash.h"
#include "target.h" #include "target.h"
#include "log.h" #include "log.h"
#include "binarybuffer.h" #include "binarybuffer.h"
#include "types.h" #include "types.h"
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <unistd.h> #include <unistd.h>
int at91sam7_register_commands(struct command_context_s *cmd_ctx); int at91sam7_register_commands(struct command_context_s *cmd_ctx);
int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank); int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
int at91sam7_erase(struct flash_bank_s *bank, int first, int last); int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last); int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count); int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
int at91sam7_probe(struct flash_bank_s *bank); int at91sam7_probe(struct flash_bank_s *bank);
int at91sam7_auto_probe(struct flash_bank_s *bank); int at91sam7_auto_probe(struct flash_bank_s *bank);
int at91sam7_erase_check(struct flash_bank_s *bank); int at91sam7_erase_check(struct flash_bank_s *bank);
int at91sam7_protect_check(struct flash_bank_s *bank); int at91sam7_protect_check(struct flash_bank_s *bank);
int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size); int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane); u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane);
void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode); void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout); u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen); int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen);
int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash = flash_driver_t at91sam7_flash =
{ {
.name = "at91sam7", .name = "at91sam7",
.register_commands = at91sam7_register_commands, .register_commands = at91sam7_register_commands,
.flash_bank_command = at91sam7_flash_bank_command, .flash_bank_command = at91sam7_flash_bank_command,
.erase = at91sam7_erase, .erase = at91sam7_erase,
.protect = at91sam7_protect, .protect = at91sam7_protect,
.write = at91sam7_write, .write = at91sam7_write,
.probe = at91sam7_probe, .probe = at91sam7_probe,
.auto_probe = at91sam7_auto_probe, .auto_probe = at91sam7_auto_probe,
.erase_check = at91sam7_erase_check, .erase_check = at91sam7_erase_check,
.protect_check = at91sam7_protect_check, .protect_check = at91sam7_protect_check,
.info = at91sam7_info .info = at91sam7_info
}; };
u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 }; u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 }; u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 }; u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"}; char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
long NVPSIZ[16] = { long NVPSIZ[16] = {
0, 0,
0x2000, /* 8K */ 0x2000, /* 8K */
0x4000, /* 16K */ 0x4000, /* 16K */
0x8000, /* 32K */ 0x8000, /* 32K */
-1, -1,
0x10000, /* 64K */ 0x10000, /* 64K */
-1, -1,
0x20000, /* 128K */ 0x20000, /* 128K */
-1, -1,
0x40000, /* 256K */ 0x40000, /* 256K */
0x80000, /* 512K */ 0x80000, /* 512K */
-1, -1,
0x100000, /* 1024K */ 0x100000, /* 1024K */
-1, -1,
0x200000, /* 2048K */ 0x200000, /* 2048K */
-1 -1
}; };
long SRAMSIZ[16] = { long SRAMSIZ[16] = {
-1, -1,
0x0400, /* 1K */ 0x0400, /* 1K */
0x0800, /* 2K */ 0x0800, /* 2K */
-1, -1,
0x1c000, /* 112K */ 0x1c000, /* 112K */
0x1000, /* 4K */ 0x1000, /* 4K */
0x14000, /* 80K */ 0x14000, /* 80K */
0x28000, /* 160K */ 0x28000, /* 160K */
0x2000, /* 8K */ 0x2000, /* 8K */
0x4000, /* 16K */ 0x4000, /* 16K */
0x8000, /* 32K */ 0x8000, /* 32K */
0x10000, /* 64K */ 0x10000, /* 64K */
0x20000, /* 128K */ 0x20000, /* 128K */
0x40000, /* 256K */ 0x40000, /* 256K */
0x18000, /* 96K */ 0x18000, /* 96K */
0x80000, /* 512K */ 0x80000, /* 512K */
}; };
int at91sam7_register_commands(struct command_context_s *cmd_ctx) int at91sam7_register_commands(struct command_context_s *cmd_ctx)
{ {
command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL); command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC, register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
"at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit"); "at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");
return ERROR_OK; return ERROR_OK;
} }
u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane) u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane)
{ {
target_t *target = bank->target; target_t *target = bank->target;
u32 fsr; u32 fsr;
target_read_u32(target, MC_FSR[flashplane], &fsr); target_read_u32(target, MC_FSR[flashplane], &fsr);
return fsr; return fsr;
} }
/** Read clock configuration and set at91sam7_info->usec_clocks*/ /** Read clock configuration and set at91sam7_info->usec_clocks*/
void at91sam7_read_clock_info(flash_bank_t *bank) void at91sam7_read_clock_info(flash_bank_t *bank)
{ {
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target; target_t *target = bank->target;
u32 mckr, mcfr, pllr; u32 mckr, mcfr, pllr;
unsigned long tmp = 0, mainfreq; unsigned long tmp = 0, mainfreq;
int flashplane; int flashplane;
/* Read main clock freqency register */ /* Read main clock freqency register */
target_read_u32(target, CKGR_MCFR, &mcfr); target_read_u32(target, CKGR_MCFR, &mcfr);
/* Read master clock register */ /* Read master clock register */
target_read_u32(target, PMC_MCKR, &mckr); target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */ /* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr); target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7_info->mck_valid = 0; at91sam7_info->mck_valid = 0;
switch (mckr & PMC_MCKR_CSS) switch (mckr & PMC_MCKR_CSS)
{ {
case 0: /* Slow Clock */ case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1; at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
tmp = mainfreq; tmp = mainfreq;
break; break;
case 1: /* Main Clock */ case 1: /* Main Clock */
if (mcfr & CKGR_MCFR_MAINRDY) if (mcfr & CKGR_MCFR_MAINRDY)
{ {
at91sam7_info->mck_valid = 1; at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
tmp = mainfreq; tmp = mainfreq;
} }
break; break;
case 2: /* Reserved */ case 2: /* Reserved */
break; break;
case 3: /* PLL Clock */ case 3: /* PLL Clock */
if (mcfr & CKGR_MCFR_MAINRDY) if (mcfr & CKGR_MCFR_MAINRDY)
{ {
target_read_u32(target, CKGR_PLLR, &pllr); target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV)) if (!(pllr & CKGR_PLLR_DIV))
break; /* 0 Hz */ break; /* 0 Hz */
at91sam7_info->mck_valid = 1; at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
/* Integer arithmetic should have sufficient precision /* Integer arithmetic should have sufficient precision
as long as PLL is properly configured. */ as long as PLL is properly configured. */
tmp = mainfreq / (pllr & CKGR_PLLR_DIV) * tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *
(((pllr & CKGR_PLLR_MUL) >> 16) + 1); (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
} }
break; break;
} }
/* Prescaler adjust */ /* Prescaler adjust */
if (((mckr & PMC_MCKR_PRES) >> 2) == 7) if (((mckr & PMC_MCKR_PRES) >> 2) == 7)
at91sam7_info->mck_valid = 0; at91sam7_info->mck_valid = 0;
else else
at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2); at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
/* Forget old flash timing */ /* Forget old flash timing */
for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++) for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++)
{ {
at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE); at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE);
} }
} }
/* Setup the timimg registers for nvbits or normal flash */ /* Setup the timimg registers for nvbits or normal flash */
void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode) void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
{ {
u32 fmr, fmcn = 0, fws = 0; u32 fmr, fmcn = 0, fws = 0;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target; target_t *target = bank->target;
if (mode && (mode != at91sam7_info->flashmode[flashplane])) if (mode && (mode != at91sam7_info->flashmode[flashplane]))
{ {
/* Always round up (ceil) */ /* Always round up (ceil) */
if (mode==FMR_TIMING_NVBITS) if (mode==FMR_TIMING_NVBITS)
{ {
if (at91sam7_info->cidr_arch == 0x60) if (at91sam7_info->cidr_arch == 0x60)
{ {
/* AT91SAM7A3 uses master clocks in 100 ns */ /* AT91SAM7A3 uses master clocks in 100 ns */
fmcn = (at91sam7_info->mck_freq/10000000ul)+1; fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
} }
else else
{ {
/* master clocks in 1uS for ARCH 0x7 types */ /* master clocks in 1uS for ARCH 0x7 types */
fmcn = (at91sam7_info->mck_freq/1000000ul)+1; fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
} }
} }
else if (mode==FMR_TIMING_FLASH) else if (mode==FMR_TIMING_FLASH)
/* main clocks in 1.5uS */ /* main clocks in 1.5uS */
fmcn = (at91sam7_info->mck_freq/666666ul)+1; fmcn = (at91sam7_info->mck_freq/666666ul)+1;
/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */ /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
if (at91sam7_info->mck_freq <= 33333ul) if (at91sam7_info->mck_freq <= 33333ul)
fmcn = 0; fmcn = 0;
/* Only allow fws=0 if clock frequency is < 30 MHz. */ /* Only allow fws=0 if clock frequency is < 30 MHz. */
if (at91sam7_info->mck_freq > 30000000ul) if (at91sam7_info->mck_freq > 30000000ul)
fws = 1; fws = 1;
DEBUG("fmcn[%i]: %i", flashplane, fmcn); DEBUG("fmcn[%i]: %i", flashplane, fmcn);
fmr = fmcn << 16 | fws << 8; fmr = fmcn << 16 | fws << 8;
target_write_u32(target, MC_FMR[flashplane], fmr); target_write_u32(target, MC_FMR[flashplane], fmr);
} }
at91sam7_info->flashmode[flashplane] = mode; at91sam7_info->flashmode[flashplane] = mode;
} }
u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout) u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
{ {
u32 status; u32 status;
while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0)) while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
{ {
DEBUG("status[%i]: 0x%x", flashplane, status); DEBUG("status[%i]: 0x%x", flashplane, status);
usleep(1000); usleep(1000);
} }
DEBUG("status[%i]: 0x%x", flashplane, status); DEBUG("status[%i]: 0x%x", flashplane, status);
if (status & 0x0C) if (status & 0x0C)
{ {
ERROR("status register: 0x%x", status); ERROR("status register: 0x%x", status);
if (status & 0x4) if (status & 0x4)
ERROR("Lock Error Bit Detected, Operation Abort"); ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8) if (status & 0x8)
ERROR("Invalid command and/or bad keyword, Operation Abort"); ERROR("Invalid command and/or bad keyword, Operation Abort");
if (status & 0x10) if (status & 0x10)
ERROR("Security Bit Set, Operation Abort"); ERROR("Security Bit Set, Operation Abort");
} }
return status; return status;
} }
/* Send one command to the AT91SAM flash controller */ /* Send one command to the AT91SAM flash controller */
int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen) int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen)
{ {
u32 fcr; u32 fcr;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target; target_t *target = bank->target;
fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
target_write_u32(target, MC_FCR[flashplane], fcr); target_write_u32(target, MC_FCR[flashplane], fcr);
DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen); DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);
if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB))) if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
{ {
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */ /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C) if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C)
{ {
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;
} }
return ERROR_OK; return ERROR_OK;
} }
if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C) if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C)
{ {
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;
} }
return ERROR_OK; return ERROR_OK;
} }
/* Read device id register, main clock frequency register and fill in driver info structure */ /* Read device id register, main clock frequency register and fill in driver info structure */
int at91sam7_read_part_info(struct flash_bank_s *bank) int at91sam7_read_part_info(struct flash_bank_s *bank)
{ {
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target; target_t *target = bank->target;
u32 cidr, status; u32 cidr, status;
int sectornum; int sectornum;
if (bank->target->state != TARGET_HALTED) if (bank->target->state != TARGET_HALTED)
{ {
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
/* Read and parse chip identification register */ /* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr); target_read_u32(target, DBGU_CIDR, &cidr);
if (cidr == 0) if (cidr == 0)
{ {
WARNING("Cannot identify target as an AT91SAM"); WARNING("Cannot identify target as an AT91SAM");
return ERROR_FLASH_OPERATION_FAILED; return ERROR_FLASH_OPERATION_FAILED;
} }
at91sam7_info->cidr = cidr; at91sam7_info->cidr = cidr;
at91sam7_info->cidr_ext = (cidr>>31)&0x0001; at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007; at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
at91sam7_info->cidr_arch = (cidr>>20)&0x00FF; at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;