Commit bc72695f authored by Committed by Matthias WelwarskyBrowse files
Lots of RISC-V improvements.
This represents months of continuing RISC-V work, with too many changes to list individually. Some improvements: * Fixed memory leaks. * Better handling of dbus timeouts. * Add `riscv expose_custom` command. * Somewhat deal with cache coherency. * Deal with more timeouts during block memory accesses. * Basic debug compliance test. * Tell gdb which watchpoint hit. * SMP support for use with -rtos hwthread * Add `riscv set_ir` Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f Signed-off-by: Tim Newsome <email@example.com> Reviewed-on: http://openocd.zylin.com/4922 Tested-by: jenkins Reviewed-by: Philipp Guehring <firstname.lastname@example.org> Reviewed-by: Liviu Ionescu <email@example.com> Reviewed-by: Matthias Welwarsky <firstname.lastname@example.org>
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