Commit ba761c13 authored by Kevin Gillespie's avatar Kevin Gillespie Committed by Kevin
Browse files

max32xxx: Cleanup, 128-bit flash, new targets.



Removing unused variable and buffer manipulation in
get_info function. Recompiling assembly files to
get propper data into write_code.

Adding support for 128-bit flash operations.

Adding configuration files for new targets. Moving common
configuration into shared file.

Change-Id: I043e861f958c6926a46735f23f6b6b466edf2a92
Signed-off-by: default avatarKevin Gillespie <kgills@gmail.com>
parent a4ac5615
/* Autogenerated with ../../../../src/helper/bin2char.sh */
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......@@ -27,44 +27,120 @@
* r0 = workarea start
* r1 = workarea end
* r2 = target address
* r3 = count (32bit words)
* r3 = count (number of writes)
* r4 = pFLASH_CTRL_BASE
*
* r5 = 128-bit write
* Clobbered:
* r5 = FLASHWRITECMD
* r6 = FLASHWRITECMD
* r7 - rp
* r8 - wp, tmp
*/
write:
/* write in 32-bit units by default */
ldr r6, [r4, #0x08] /* FLSH_CN */
orr r6, r6, #0x10 /* Width 32 bits */
str r6, [r4, #0x08] /* FLSH_CN */
tst r5, #1 /* Check 32-bit write options */
beq wait_fifo
/* Enable 128-bit write */
ldr r6, [r4, #0x08] /* FLSH_CN */
bic r6, r6, #0x10 /* Width 128 bits */
str r6, [r4, #0x08] /* FLSH_CN */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
ldr r8, [r0, #0x00] /* read wp */
cmp r8, #0x00 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #0x04] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
mainloop:
str r2, [r4, #0x00] /* FLSH_ADDR - write address */
add r2, r2, #4 /* increment target address */
ldr r8, [r7], #4
str r8, [r4, #0x30] /* FLSH_DATA0 - write data */
ldr r5, [r4, #0x08] /* FLSH_CN */
orr r5, r5, #1
str r5, [r4, #0x08] /* FLSH_CN - enable write */
str r2, [r4, #0x00] /* FLSH_ADDR - write address */
add r2, r2, #0x04 /* increment target address */
tst r5, #1 /* Check 32-bit write options */
beq inc32
add r2, r2, #0x0C /* additional 12 if 128-bit write*/
inc32:
ldr r8, [r7], #0x04
str r8, [r4, #0x30] /* FLSH_DATA0 - write data */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #0x08 /* skip loader args */
str r7, [r0, #0x04] /* store rp */
tst r5, #1 /* Check 32-bit write options */
beq write32
wait_fifo0:
ldr r8, [r0, #0x00] /* read wp */
cmp r8, #0x00 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #0x04] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo0
ldr r8, [r7], #0x04
str r8, [r4, #0x34] /* FLSH_DATA1 - write data */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #0x08 /* skip loader args */
str r7, [r0, #0x04] /* store rp */
wait_fifo1:
ldr r8, [r0, #0x00] /* read wp */
cmp r8, #0x00 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #0x04] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo1
ldr r8, [r7], #0x04
str r8, [r4, #0x38] /* FLSH_DATA2 - write data */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #0x08 /* skip loader args */
str r7, [r0, #0x04] /* store rp */
wait_fifo2:
ldr r8, [r0, #0x00] /* read wp */
cmp r8, #0x00 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #0x04] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo2
ldr r8, [r7], #0x04
str r8, [r4, #0x3C] /* FLSH_DATA3 - write data */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #0x08 /* skip loader args */
str r7, [r0, #0x04] /* store rp */
write32:
ldr r6, [r4, #0x08] /* FLSH_CN */
orr r6, r6, #0x01 /* WE */
str r6, [r4, #0x08] /* FLSH_CN - enable write */
busy:
ldr r8, [r4, #0x08] /* FLSH_CN */
tst r8, #1
bne busy
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement word count */
cbz r3, exit /* loop if not done */
b wait_fifo
ldr r8, [r4, #0x08] /* FLSH_CN */
tst r8, #0x07
bne busy
subs r3, r3, #0x01 /* decrement write count */
cbz r3, exit /* loop if not done */
b wait_fifo
exit:
bkpt
/* restore flash settings */
ldr r6, [r4, #0x08] /* FLSH_CN */
orr r6, r6, #0x10 /* Width 32 bits */
str r6, [r4, #0x08] /* FLSH_CN */
bkpt
This diff is collapsed.
# Maxim Integrated MAX32620 OpenOCD target configuration file
# www.maximintegrated.com
# adapter speed
adapter_khz 4000
# reset pin configuration
# Set the reset pin configuration
reset_config srst_only
adapter_nsrst_delay 200
if {[using_jtag]} {
jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
} else {
swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
}
# Set flash parameters
set FLASH_BASE 0x0
set FLASH_SIZE 0x200000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 32
# target configuration
target create max32620.cpu cortex_m -chain-position max32620.cpu
max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
# Setup the reserved TAP
set RSV_TAP 1
# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
# max32620 flash base address 0x00000000
# max32620 flash size 0x200000 (2MB)
# max32620 FLC base address 0x40002000
# max32620 sector (page) size 0x2000 (8kB)
# max32620 clock speed 96 (MHz)
flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
source [find target/max32xxx.cfg]
# Maxim Integrated MAX32625 OpenOCD target configuration file
# www.maximintegrated.com
# adapter speed
adapter_khz 4000
# reset pin configuration
# Set the reset pin configuration
reset_config srst_only
adapter_nsrst_delay 200
if {[using_jtag]} {
jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
} else {
swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
}
# Set flash parameters
set FLASH_BASE 0x0
set FLASH_SIZE 0x80000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 32
# target configuration
target create max32625.cpu cortex_m -chain-position max32625.cpu
max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
# Setup the reserved TAP
set RSV_TAP 1
# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
# max32625 flash base address 0x00000000
# max32625 flash size 0x80000 (512k)
# max32625 FLC base address 0x40002000
# max32625 sector (page) size 0x2000 (8kB)
# max32625 clock speed 96 (MHz)
flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
source [find target/max32xxx.cfg]
# Maxim Integrated MAX3263X OpenOCD target configuration file
# www.maximintegrated.com
# adapter speed
adapter_khz 4000
# Set the reset pin configuration
reset_config none
# reset pin configuration
reset_config srst_only
# Set flash parameters
set FLASH_BASE 0x0
set FLASH_SIZE 0x200000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 32
if {[using_jtag]} {
jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
} else {
swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
}
# Setup the reserved TAP
set RSV_TAP 1
source [find target/max32xxx.cfg]
# Create custom reset sequence
$_CHIPNAME.cpu configure -event reset-init {
# Reset the peripherals
mww 0x40000848 0xFFFFFFFF
mww 0x4000084C 0xFFFFFFFF
# target configuration
target create max3263x.cpu cortex_m -chain-position max3263x.cpu
max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
# max3263x flash base address 0x00000000
# max3263x flash size 0x200000 (2MB)
# max3263x FLC base address 0x40002000
# max3263x sector (page) size 0x2000 (8kB)
# max3263x clock speed 96 (MHz)
flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
sleep 10
mww 0x40000848 0x0
mww 0x4000084C 0x0
# Reset the SP
set SP_ADDR [mrw 0x4]
reg sp $SP_ADDR
# Reset the PC to the Reset_Handler
set RESET_HANDLER_ADDR [mrw 0x4]
reg pc $RESET_HANDLER_ADDR
}
# Maxim Integrated MAX32650 OpenOCD target configuration file
# www.maximintegrated.com
# Set the reset pin configuration
reset_config srst_only
adapter_nsrst_delay 200
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x300000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 32
# set FLASH_BITS 128
source [find target/max32xxx.cfg]
# Maxim Integrated MAX32660 OpenOCD target configuration file
# www.maximintegrated.com
# Set the reset pin configuration
reset_config srst_only
adapter_nsrst_delay 200
# Set flash parameters
set FLASH_BASE 0x0
set FLASH_SIZE 0x40000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 32
# set FLASH_BITS 128
source [find target/max32xxx.cfg]
# Maxim Integrated MAX32665 OpenOCD target configuration file
# www.maximintegrated.com
# Set the reset pin configuration
reset_config srst_only
adapter_nsrst_delay 200
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x300000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_BITS 128
source [find target/max32xxx.cfg]
# Maxim Integrated max32xxx OpenOCD drver configuration file
# www.maximintegrated.com
source [find mem_helper.tcl]
source [find target/swj-dp.tcl]
# Set the adapter speed
if { [info exists ADAPTER_KHZ] } {
set _ADAPTER_KHZ $ADAPTER_KHZ
} else {
set _ADAPTER_KHZ 2000
}
adapter_khz $_ADAPTER_KHZ
# Target configuration
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME max32xxx
}
# Add reserved TAP
if { [using_jtag] && [info exists RSV_TAP] } {
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
} else {
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
}
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap
# Setup working area
if { [info exists WORK_START] } {
set _WORK_START $WORK_START
} else {
set _WORK_START 0x20005000
}
if { [info exists WORK_SIZE] } {
set _WORK_SIZE $WORK_SIZE
} else {
set _WORK_SIZE 0x2000
}
$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE
# Configure flash driver
if { [info exists FLASH_BASE] } {
set _FLASH_BASE $FLASH_BASE
} else {
set _FLASH_BASE 0x10000000
}
if { [info exists FLASH_SIZE] } {
set _FLASH_SIZE $FLASH_SIZE
} else {
set _FLASH_SIZE 0x10000
}
if { [info exists FLC_BASE] } {
set _FLC_BASE $FLC_BASE
} else {
set _FLC_BASE 0x40029000
}
if { [info exists FLASH_SECTOR] } {
set _FLASH_SECTOR $FLASH_SECTOR
} else {
set _FLASH_SECTOR 0x2000
}
if { [info exists FLASH_CLK] } {
set _FLASH_CLK $FLASH_CLK
} else {
set _FLASH_CLK 96
}
if { [info exists FLASH_BITS] } {
set _FLASH_BITS $FLASH_BITS
} else {
set _FLASH_BITS 32
}
flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_BITS
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