Commit b0d04ab6 authored by mlu's avatar mlu
Browse files

Changed armv7m and cortexm3 to use nev arm_adi_v5 instead of cortex_swjdp.

Added support for accessport ROM table identification, dap command. 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 573d9a03
...@@ -11,12 +11,12 @@ AM_CPPFLAGS = -DPKGLIBDIR=\"$(pkglibdir)\" @CPPFLAGS@ ...@@ -11,12 +11,12 @@ AM_CPPFLAGS = -DPKGLIBDIR=\"$(pkglibdir)\" @CPPFLAGS@
noinst_LIBRARIES = libtarget.a noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \ libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \ arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \ arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \ etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
mips32_pracc.c mips32_dmaacc.c mips_ejtag.c mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \ arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \ arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
nobase_dist_pkglib_DATA = nobase_dist_pkglib_DATA =
......
...@@ -550,6 +550,12 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) ...@@ -550,6 +550,12 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
int armv7m_register_commands(struct command_context_s *cmd_ctx) int armv7m_register_commands(struct command_context_s *cmd_ctx)
{ {
command_t *arm_adi_v5_dap_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
return ERROR_OK; return ERROR_OK;
} }
...@@ -695,3 +701,45 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u ...@@ -695,3 +701,45 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u
return ERROR_OK; return ERROR_OK;
} }
int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 apsel, apid;
int retval;
apsel = 0;
if (argc > 0)
{
apsel = strtoul(args[0], NULL, 0);
}
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
retval = swjdp_transaction_endcheck(swjdp);
command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
return retval;
}
int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
u32 apsel;
apsel = 0;
if (argc > 0)
{
apsel = strtoul(args[0], NULL, 0);
}
retval = dap_info_command(cmd_ctx, swjdp, apsel);
return retval;
}
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include "register.h" #include "register.h"
#include "target.h" #include "target.h"
#include "arm_jtag.h" #include "arm_jtag.h"
#include "arm_adi_v5.h"
/* define for enabling armv7 gdb workarounds */ /* define for enabling armv7 gdb workarounds */
#if 1 #if 1
...@@ -78,6 +79,8 @@ typedef struct armv7m_common_s ...@@ -78,6 +79,8 @@ typedef struct armv7m_common_s
reg_cache_t *core_cache; reg_cache_t *core_cache;
enum armv7m_mode core_mode; enum armv7m_mode core_mode;
int exception_number; int exception_number;
swjdp_common_t swjdp_info;
/* Direct processor core register read and writes */ /* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value); int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
......
This diff is collapsed.
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#include "register.h" #include "register.h"
#include "target.h" #include "target.h"
#include "armv7m.h" #include "armv7m.h"
#include "cortex_swjdp.h" //#include "arm_adi_v5.h"
extern char* cortex_m3_state_strings[]; extern char* cortex_m3_state_strings[];
...@@ -162,7 +162,7 @@ typedef struct cortex_m3_common_s ...@@ -162,7 +162,7 @@ typedef struct cortex_m3_common_s
u32 *intsetenable; u32 *intsetenable;
armv7m_common_t armv7m; armv7m_common_t armv7m;
swjdp_common_t swjdp_info; // swjdp_common_t swjdp_info;
void *arch_info; void *arch_info;
} cortex_m3_common_t; } cortex_m3_common_t;
...@@ -188,7 +188,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin ...@@ -188,7 +188,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx); //extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap); extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
#endif /* CORTEX_M3_H */ #endif /* CORTEX_M3_H */
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