Commit ad751bb7 authored by oharboe's avatar oharboe
Browse files

John McCarthy <jgmcc@magma.ca> pic32mx flash wip

git-svn-id: svn://svn.berlios.de/openocd/trunk@1296 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 9d75343e
......@@ -4,7 +4,7 @@ METASOURCES = AUTO
noinst_LIBRARIES = libflash.a
libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c at91sam7_old.c str7x.c str9x.c aduc702x.c nand.c lpc3180_nand_controller.c \
stellaris.c str9xpec.c stm32x.c tms470.c ecos.c \
s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c
s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c
noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h at91sam7_old.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
stellaris.h str9xpec.h stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h mflash.h \
ocl.h
ocl.h pic32mx.h
......@@ -78,6 +78,7 @@ extern flash_driver_t tms470_flash;
extern flash_driver_t ecosflash_flash;
extern flash_driver_t lpc288x_flash;
extern flash_driver_t ocl_flash;
extern flash_driver_t pic32mx_flash;
flash_driver_t *flash_drivers[] = {
&lpc2000_flash,
......@@ -94,6 +95,7 @@ flash_driver_t *flash_drivers[] = {
&ecosflash_flash,
&lpc288x_flash,
&ocl_flash,
&pic32mx_flash,
NULL,
};
......@@ -316,14 +318,17 @@ int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
/* put flash bank in linked list */
if (flash_banks)
{
int bank_num = 0;
/* find last flash bank */
for (p = flash_banks; p && p->next; p = p->next);
for (p = flash_banks; p && p->next; p = p->next) bank_num++;
if (p)
p->next = c;
c->bank_number = bank_num + 1;
}
else
{
flash_banks = c;
c->bank_number = 0;
}
found = 1;
......
This diff is collapsed.
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2008 by John McCarthy *
* jgmcc@magma.ca *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef PIC32MX_H
#define PIC32MX_H
#include "flash.h"
#include "target.h"
typedef struct pic32mx_flash_bank_s
{
working_area_t *write_algorithm;
int devid;
int ppage_size;
int probed;
} pic32mx_flash_bank_t;
#define PIC32MX_MANUF_ID 0x029
/* pic32mx memory locations */
#define PIC32MX_KUSEG_PGM_FLASH 0x7D000000
#define PIC32MX_KUSEG_RAM 0x7F000000
#define PIC32MX_KSEG0_RAM 0x80000000
#define PIC32MX_KSEG0_PGM_FLASH 0x9D000000
#define PIC32MX_KSEG0_BOOT_FLASH 0x9FC00000
#define PIC32MX_KSEG1_RAM 0xA0000000
#define PIC32MX_KSEG1_PGM_FLASH 0xBD000000
#define PIC32MX_KSEG1_PERIPHERAL 0xBF800000
#define PIC32MX_KSEG1_BOOT_FLASH 0xBFC00000
#define PIC32MX_PHYS_RAM 0x00000000
#define PIC32MX_PHYS_PGM_FLASH 0x1D000000
#define PIC32MX_PHYS_PERIPHERALS 0x1F800000
#define PIC32MX_PHYS_BOOT_FLASH 0x1FC00000
/* pic32mx configuration register locations */
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define PIC32MX_DEVCFG3 0XBFC02FF0
#define PIC32MX_DEVID 0xBF80F220
/* pic32mx flash controller register locations */
#define PIC32MX_NVMCON 0xBF80F400
#define PIC32MX_NVMCONCLR 0xBF80F404
#define PIC32MX_NVMCONSET 0xBF80F408
#define PIC32MX_NVMCONINV 0xBF80F40C
#define NVMCON_NVMWR (1<<15)
#define NVMCON_NVMWREN (1<<14)
#define NVMCON_NVMERR (1<<13)
#define NVMCON_LVDERR (1<<12)
#define NVMCON_LVDSTAT (1<<11)
#define NVMCON_OP_PFM_ERASE 0x5
#define NVMCON_OP_PAGE_ERASE 0x4
#define NVMCON_OP_ROW_PROG 0x3
#define NVMCON_OP_WORD_PROG 0x1
#define NVMCON_OP_NOP 0x0
#define PIC32MX_NVMKEY 0xBF80F410
#define PIC32MX_NVMADDR 0xBF80F420
#define PIC32MX_NVMADDRCLR 0xBF80F424
#define PIC32MX_NVMADDRSET 0xBF80F428
#define PIC32MX_NVMADDRINV 0xBF80F42C
#define PIC32MX_NVMDATA 0xBF80F430
#define PIC32MX_NVMSRCADDR 0xBF80F440
/* flash unlock keys */
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
typedef struct pic32mx_mem_layout_s {
u32 sector_start;
u32 sector_size;
} pic32mx_mem_layout_t;
#endif /* PIC32MX_H */
# The Olimex PIC-P32MX has a PIC32MX
set CPUTAPID 0x40916053
source [find target/pic32mx.cfg]
init
flash probe 0
flash probe 1
......@@ -102,6 +102,7 @@ typedef struct mips_ejtag_s
{
jtag_tap_t *tap;
u32 impcode;
u32 idcode;
/*int use_dma;*/
u32 ejtag_ctrl;
} mips_ejtag_t;
......
......@@ -50,6 +50,7 @@ int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
int mips_m4k_examine(struct target_s *target);
int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
target_type_t mips_m4k_target =
{
......@@ -73,7 +74,7 @@ target_type_t mips_m4k_target =
.read_memory = mips_m4k_read_memory,
.write_memory = mips_m4k_write_memory,
.bulk_write_memory = mips_m4k_bulk_write_memory,
.checksum_memory = NULL,
.checksum_memory = mips_m4k_checksum_memory,
.blank_check_memory = NULL,
.run_algorithm = mips32_run_algorithm,
......@@ -766,7 +767,8 @@ int mips_m4k_examine(struct target_s *target)
if (!target->type->examined)
{
mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
ejtag_info->idcode = idcode;
if (((idcode >> 1) & 0x7FF) == 0x29)
{
/* we are using a pic32mx so select ejtag port
......@@ -790,3 +792,8 @@ int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
{
return mips_m4k_write_memory(target, address, 4, count, buffer);
}
int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
{
return ERROR_FAIL; /* use bulk read method */
}
......@@ -26,13 +26,15 @@ reset_config srst_only
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CPUNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
flash bank pic32mx 0xbd000000 0 0 0 0
flash bank pic32mx 0xbfc00000 0 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
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