Commit a931baa6 authored by kc8apf's avatar kc8apf
Browse files

Whitespace cleanup from David Brownell <david-b@pacbell.net>

git-svn-id: svn://svn.berlios.de/openocd/trunk@1802 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 41826d5b
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This diff is collapsed.
......@@ -99,7 +99,7 @@ enum
typedef struct nand_manufacturer_s
{
int id;
int id;
char *name;
} nand_manufacturer_t;
......@@ -115,43 +115,43 @@ typedef struct nand_info_s
/* Option constants for bizarre disfunctionality and real features
*/
enum {
enum {
/* Chip can not auto increment pages */
NAND_NO_AUTOINCR = 0x00000001,
/* Buswitdh is 16 bit */
NAND_BUSWIDTH_16 = 0x00000002,
/* Device supports partial programming without padding */
NAND_NO_PADDING = 0x00000004,
/* Chip has cache program function */
NAND_CACHEPRG = 0x00000008,
/* Chip has copy back function */
NAND_COPYBACK = 0x00000010,
/* AND Chip which has 4 banks and a confusing page / block
* assignment. See Renesas datasheet for further information */
NAND_IS_AND = 0x00000020,
/* Chip has a array of 4 pages which can be read without
* additional ready /busy waits */
NAND_4PAGE_ARRAY = 0x00000040,
/* Chip requires that BBT is periodically rewritten to prevent
* bits from adjacent blocks from 'leaking' in altering data.
* This happens with the Renesas AG-AND chips, possibly others. */
BBT_AUTO_REFRESH = 0x00000080,
/* Chip does not require ready check on read. True
* for all large page devices, as they do not support
* autoincrement.*/
NAND_NO_READRDY = 0x00000100,
/* Options valid for Samsung large page devices */
NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
/* Options for new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes
*/
......@@ -175,7 +175,7 @@ enum
NAND_CMD_READID = 0x90,
NAND_CMD_ERASE2 = 0xd0,
NAND_CMD_RESET = 0xff,
/* Extended commands for large page devices */
NAND_CMD_READSTART = 0x30,
NAND_CMD_RNDOUTSTART = 0xE0,
......@@ -198,7 +198,7 @@ enum oob_formats
NAND_OOB_NONE = 0x0, /* no OOB data at all */
NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
NAND_OOB_ONLY = 0x2, /* only OOB data */
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
......
......@@ -59,7 +59,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
......@@ -70,7 +70,7 @@ static int s3c2410_nand_device_command(struct command_context_s *cmd_ctx, char *
info->addr = S3C2410_NFADDR;
info->data = S3C2410_NFDATA;
info->nfstat = S3C2410_NFSTAT;
return ERROR_OK;
}
......@@ -79,7 +79,7 @@ static int s3c2410_init(struct nand_device_s *device)
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
target_write_u32(target, S3C2410_NFCONF,
S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) |
S3C2410_NFCONF_TWRPH0(5) | S3C2410_NFCONF_TWRPH1(3));
......@@ -95,7 +95,7 @@ static int s3c2410_write_data(struct nand_device_s *device, u16 data)
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
target_write_u32(target, S3C2410_NFDATA, data);
return ERROR_OK;
}
......@@ -104,13 +104,13 @@ static int s3c2410_read_data(struct nand_device_s *device, void *data)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
target_read_u8(target, S3C2410_NFDATA, data);
target_read_u8(target, S3C2410_NFDATA, data);
return ERROR_OK;
}
......@@ -124,14 +124,14 @@ static int s3c2410_nand_ready(struct nand_device_s *device, int timeout)
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
do {
target_read_u8(target, S3C2410_NFSTAT, &status);
if (status & S3C2410_NFSTAT_BUSY)
return 1;
alive_sleep(1);
alive_sleep(1);
} while (timeout-- > 0);
return 0;
......
......@@ -69,7 +69,7 @@ static int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2412_NFSTAT;
return ERROR_OK;
}
......
......@@ -59,7 +59,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
......@@ -70,7 +70,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2440_NFSTAT;
return ERROR_OK;
}
......@@ -100,10 +100,10 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout)
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
do {
do {
target_read_u8(target, s3c24xx_info->nfstat, &status);
if (status & S3C2440_NFSTAT_READY)
return 1;
......@@ -130,7 +130,7 @@ int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_siz
return ERROR_NAND_OPERATION_FAILED;
}
while (data_size >= 4) {
while (data_size >= 4) {
target_read_u32(target, nfdata, &tmp);
data[0] = tmp;
......@@ -164,7 +164,7 @@ int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_si
return ERROR_NAND_OPERATION_FAILED;
}
while (data_size >= 4) {
while (data_size >= 4) {
tmp = le_to_h_u32(data);
target_write_u32(target, nfdata, tmp);
......
......@@ -58,7 +58,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
......@@ -69,7 +69,7 @@ static int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2412_NFSTAT;
return ERROR_OK;
}
......
......@@ -37,7 +37,7 @@ s3c24xx_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *s3c24xx_info;
s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
if (s3c24xx_info == NULL) {
LOG_ERROR("no memory for nand controller\n");
......@@ -69,9 +69,9 @@ int s3c24xx_reset(struct nand_device_s *device)
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
target_write_u32(target, s3c24xx_info->cmd, 0xff);
return ERROR_OK;
}
......@@ -79,7 +79,7 @@ int s3c24xx_command(struct nand_device_s *device, u8 command)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
......@@ -94,12 +94,12 @@ int s3c24xx_address(struct nand_device_s *device, u8 address)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
target_write_u16(target, s3c24xx_info->addr, address);
return ERROR_OK;
}
......@@ -113,7 +113,7 @@ int s3c24xx_write_data(struct nand_device_s *device, u16 data)
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
target_write_u8(target, s3c24xx_info->data, data);
return ERROR_OK;
}
......@@ -122,7 +122,7 @@ int s3c24xx_read_data(struct nand_device_s *device, void *data)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
......
......@@ -30,12 +30,12 @@
typedef struct s3c24xx_nand_controller_s
{
struct target_s *target;
/* register addresses */
u32 cmd;
u32 addr;
u32 data;
u32 nfstat;
u32 nfstat;
} s3c24xx_nand_controller_t;
/* Default to using the un-translated NAND register based address */
......
......@@ -47,7 +47,6 @@ typedef struct stellaris_flash_bank_s
u32 rcc;
u8 mck_valid;
u32 mck_freq;
} stellaris_flash_bank_t;
/* STELLARIS control registers */
......@@ -66,7 +65,7 @@ typedef struct stellaris_flash_bank_s
#define FMPRE 0x130
#define FMPPE 0x134
#define USECRL 0x140
#define USECRL 0x140
#define FLASH_CONTROL_BASE 0x400FD000
#define FLASH_FMA (FLASH_CONTROL_BASE|0x000)
......@@ -87,7 +86,7 @@ typedef struct stellaris_flash_bank_s
#define FMC_COMT (1<<3)
#define FMC_MERASE (1<<2)
#define FMC_ERASE (1<<1)
#define FMC_WRITE (1<<0)
#define FMC_WRITE (1<<0)
/* STELLARIS constants */
......
......@@ -66,17 +66,17 @@ typedef struct stm32x_flash_bank_s
#define FLASH_PG (1<<0)
#define FLASH_PER (1<<1)
#define FLASH_MER (1<<2)
#define FLASH_MER (1<<2)
#define FLASH_OPTPG (1<<4)
#define FLASH_OPTER (1<<5)
#define FLASH_STRT (1<<6)
#define FLASH_LOCK (1<<7)
#define FLASH_OPTWRE (1<<9)
/* FLASH_SR regsiter bits */
/* FLASH_SR register bits */
#define FLASH_BSY (1<<0)
#define FLASH_PGERR (1<<2)
#define FLASH_PGERR (1<<2)
#define FLASH_WRPRTERR (1<<4)
#define FLASH_EOP (1<<5)
......
......@@ -59,14 +59,14 @@ enum str7x_status_codes
#define FLASH_AR 0x00000010
#define FLASH_ER 0x00000014
#define FLASH_NVWPAR 0x0000DFB0
#define FLASH_NVAPR0 0x0000DFB8
#define FLASH_NVAPR1 0x0000DFBC
#define FLASH_NVAPR0 0x0000DFB8
#define FLASH_NVAPR1 0x0000DFBC
/* FLASH_CR0 register bits */
#define FLASH_WMS 0x80000000
#define FLASH_SUSP 0x40000000
#define FLASH_WPG 0x20000000
#define FLASH_WPG 0x20000000
#define FLASH_DWPG 0x10000000
#define FLASH_SER 0x08000000
#define FLASH_SPR 0x01000000
......@@ -76,7 +76,7 @@ enum str7x_status_codes
#define FLASH_BSYA1 0x00000004
#define FLASH_BSYA0 0x00000002
/* FLASH_CR1 regsiter bits */
/* FLASH_CR1 register bits */
#define FLASH_B1S 0x02000000
#define FLASH_B0S 0x01000000
......
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