Commit a3325f1d authored by ntfreak's avatar ntfreak
Browse files

- added missing parport configs to texi

- remove spaces from last patch

git-svn-id: svn://svn.berlios.de/openocd/trunk@951 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 7e94e2e8
...@@ -437,13 +437,20 @@ Currently supported cables are ...@@ -437,13 +437,20 @@ Currently supported cables are
@cindex wiggler @cindex wiggler
The original Wiggler layout, also supported by several clones, such The original Wiggler layout, also supported by several clones, such
as the Olimex ARM-JTAG as the Olimex ARM-JTAG
@item @b{wiggler2}
@cindex wiggler2
Same as original wiggler except an led is fitted on D5.
@item @b{wiggler_ntrst_inverted}
@cindex wiggler_ntrst_inverted
Same as original wiggler except TRST is inverted.
@item @b{old_amt_wiggler} @item @b{old_amt_wiggler}
@cindex old_amt_wiggler @cindex old_amt_wiggler
The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
version available from the website uses the original Wiggler layout ('@var{wiggler}') version available from the website uses the original Wiggler layout ('@var{wiggler}')
@item @b{chameleon} @item @b{chameleon}
@cindex chameleon @cindex chameleon
The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target. The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
program the Chameleon itself, not a connected target.
@item @b{dlc5} @item @b{dlc5}
@cindex dlc5 @cindex dlc5
The Xilinx Parallel cable III. The Xilinx Parallel cable III.
...@@ -455,6 +462,13 @@ This is also the layout used by the HollyGates design ...@@ -455,6 +462,13 @@ This is also the layout used by the HollyGates design
@item @b{flashlink} @item @b{flashlink}
@cindex flashlink @cindex flashlink
The ST Parallel cable. The ST Parallel cable.
@item @b{arm-jtag}
@cindex arm-jtag
Same as original wiggler except SRST and TRST connections reversed and
TRST is also inverted.
@item @b{altium}
@cindex altium
Altium Universal JTAG cable.
@end itemize @end itemize
@item @b{parport_write_on_exit} <@var{on|off}> @item @b{parport_write_on_exit} <@var{on|off}>
@cindex parport_write_on_exit @cindex parport_write_on_exit
......
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