Commit 95423183 authored by oharboe's avatar oharboe
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Rolf Meeser <> adds flash support for NXP's LPC2900 family (ARM968E).

git-svn-id: svn:// b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 6d2473b6
......@@ -3309,7 +3309,15 @@ and executed.
@deffn {Flash Driver} lpc2000
Most members of the LPC1700 and LPC2000 microcontroller families from NXP
include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
@quotation Note
There are LPC2000 devices which are not supported by the @var{lpc2000}
The LPC2888 is supported by the @var{lpc288x} driver.
The LPC29xx family is supported by the @var{lpc2900} driver.
@end quotation
The @var{lpc2000} driver defines two mandatory and one optional parameters,
which must appear in the following order:
......@@ -3349,6 +3357,129 @@ flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
@end example
@end deffn
@deffn {Flash Driver} lpc2900
This driver supports the LPC29xx ARM968E based microcontroller family
from NXP.
The predefined parameters @var{base}, @var{size}, @var{chip_width} and
@var{bus_width} of the @code{flash bank} command are ignored. Flash size and
sector layout are auto-configured by the driver.
The driver has one additional mandatory parameter: The CPU clock rate
(in kHz) at the time the flash operations will take place. Most of the time this
will not be the crystal frequency, but a higher PLL frequency. The
@code{reset-init} event handler in the board script is usually the place where
you start the PLL.
The driver rejects flashless devices (currently the LPC2930).
The EEPROM in LPC2900 devices is not mapped directly into the address space.
It must be handled much more like NAND flash memory, and will therefore be
handled by a separate @code{lpc2900_eeprom} driver (not yet available).
Sector protection in terms of the LPC2900 is handled transparently. Every time a
sector needs to be erased or programmed, it is automatically unprotected.
What is shown as protection status in the @code{flash info} command, is
actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
sector from ever being erased or programmed again. As this is an irreversible
mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
and not by the standard @code{flash protect} command.
Example for a 125 MHz clock frequency:
flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
@end example
Some @code{lpc2900}-specific commands are defined. In the following command list,
the @var{bank} parameter is the bank number as obtained by the
@code{flash banks} command.
@deffn Command {lpc2900 signature} bank
Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
content. This is a hardware feature of the flash block, hence the calculation is
very fast. You may use this to verify the content of a programmed device against
a known signature.
lpc2900 signature 0
signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
@end example
@end deffn
@deffn Command {lpc2900 read_custom} bank filename
Reads the 912 bytes of customer information from the flash index sector, and
saves it to a file in binary format.
lpc2900 read_custom 0 /path_to/customer_info.bin
@end example
@end deffn
The index sector of the flash is a @emph{write-only} sector. It cannot be
erased! In order to guard against unintentional write access, all following
commands need to be preceeded by a successful call to the @code{password}
@deffn Command {lpc2900 password} bank password
You need to use this command right before each of the following commands:
@code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
@code{lpc2900 secure_jtag}.
The password string is fixed to "I_know_what_I_am_doing".
lpc2900 password 0 I_know_what_I_am_doing
Potentially dangerous operation allowed in next command!
@end example
@end deffn
@deffn Command {lpc2900 write_custom} bank filename type
Writes the content of the file into the customer info space of the flash index
sector. The filetype can be specified with the @var{type} field. Possible values
for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
@var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
contain a single section, and the contained data length must be exactly
912 bytes.
@quotation Attention
This cannot be reverted! Be careful!
@end quotation
lpc2900 write_custom 0 /path_to/customer_info.bin bin
@end example
@end deffn
@deffn Command {lpc2900 secure_sector} bank first last
Secures the sector range from @var{first} to @var{last} (including) against
further program and erase operations. The sector security will be effective
after the next power cycle.
@quotation Attention
This cannot be reverted! Be careful!
@end quotation
Secured sectors appear as @emph{protected} in the @code{flash info} command.
lpc2900 secure_sector 0 1 1
flash info 0
#0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
# 0: 0x00000000 (0x2000 8kB) not protected
# 1: 0x00002000 (0x2000 8kB) protected
# 2: 0x00004000 (0x2000 8kB) not protected
@end example
@end deffn
@deffn Command {lpc2900 secure_jtag} bank
Irreversibly disable the JTAG port. The new JTAG security setting will be
effective after the next power cycle.
@quotation Attention
This cannot be reverted! Be careful!
@end quotation
lpc2900 secure_jtag 0
@end example
@end deffn
@end deffn
@deffn {Flash Driver} ocl
@emph{No idea what this is, other than using some arm7/arm9 core.}
......@@ -9,6 +9,8 @@ libflash_la_SOURCES = \
arm_nandio.c \
flash.c \
lpc2000.c \
lpc288x.c \
lpc2900.c \
cfi.c \
non_cfi.c \
at91sam7.c \
......@@ -32,7 +34,6 @@ libflash_la_SOURCES = \
s3c2412_nand.c \
s3c2440_nand.c \
s3c2443_nand.c \
lpc288x.c \
ocl.c \
mflash.c \
pic32mx.c \
......@@ -43,6 +44,8 @@ noinst_HEADERS = \
arm_nandio.h \
flash.h \
lpc2000.h \
lpc288x.h \
lpc2900.h \
cfi.h \
non_cfi.h \
at91sam7.h \
......@@ -57,7 +60,6 @@ noinst_HEADERS = \
tms470.h \
s3c24xx_nand.h \
s3c24xx_regs_nand.h \
lpc288x.h \
mflash.h \
ocl.h \
pic32mx.h \
......@@ -47,6 +47,8 @@ static int handle_flash_protect_command(struct command_context_s *cmd_ctx, char
/* flash drivers
extern flash_driver_t lpc2000_flash;
extern flash_driver_t lpc288x_flash;
extern flash_driver_t lpc2900_flash;
extern flash_driver_t cfi_flash;
extern flash_driver_t at91sam3_flash;
extern flash_driver_t at91sam7_flash;
......@@ -58,13 +60,14 @@ extern flash_driver_t str9xpec_flash;
extern flash_driver_t stm32x_flash;
extern flash_driver_t tms470_flash;
extern flash_driver_t ecosflash_flash;
extern flash_driver_t lpc288x_flash;
extern flash_driver_t ocl_flash;
extern flash_driver_t pic32mx_flash;
extern flash_driver_t avr_flash;
flash_driver_t *flash_drivers[] = {
......@@ -76,7 +79,6 @@ flash_driver_t *flash_drivers[] = {
This diff is collapsed.
* Copyright (C) 2009 by *
* Rolf Meeser <> *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#ifndef lpc2900_H
#define lpc2900_H
#include "flash.h"
#endif /* lpc2900_H */
# Hitex eval board for LPC2929/LPC2939
# Delays on reset lines
jtag_nsrst_delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
jtag_khz 2000
# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
# HAS_ETB Must be set to 1. The CPU on this board has ETB.
# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
set HAS_ETB 1
set FLASH_CLOCK 112000
source [find target/lpc2900.cfg]
# A working area will help speeding the flash programming
#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
# Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
jtag_khz 2000
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
$_TARGETNAME configure -event reset-init {
# Flash
mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached
# Use PLL
mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz
mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal
mww 0xFFFF8028 0x00000005 # PLL: (power down)
mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up)
# --> f=112 MHz, fcco=224 MHz
sleep 100
mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
# Increase JTAG speed
jtag_khz 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F # P1.14 = D0
mww 0xE000113C 0x0000001F # P1.15 = D1
mww 0xE0001140 0x0000001F # P1.16 = D2
mww 0xE0001144 0x0000001F # P1.17 = D3
mww 0xE0001148 0x0000001F # P1.18 = D4
mww 0xE000114C 0x0000001F # P1.19 = D5
mww 0xE0001150 0x0000001F # P1.20 = D6
mww 0xE0001154 0x0000001F # P1.21 = D7
mww 0xE0001200 0x0000001F # P2.0 = D8
mww 0xE0001204 0x0000001F # P2.1 = D9
mww 0xE0001208 0x0000001F # P2.2 = D10
mww 0xE000120C 0x0000001F # P2.3 = D11
mww 0xE0001210 0x0000001F # P2.4 = D12
mww 0xE0001214 0x0000001F # P2.5 = D13
mww 0xE0001218 0x0000001F # P2.6 = D14
mww 0xE000121C 0x0000001F # P2.7 = D15
mww 0xE0001104 0x00000007 # P1.1 = A1
mww 0xE0001108 0x00000007 # P1.2 = A2
mww 0xE000110C 0x00000007 # P1.3 = A3
mww 0xE0001110 0x00000007 # P1.4 = A4
mww 0xE0001114 0x00000007 # P1.5 = A5
mww 0xE0001118 0x00000007 # P1.6 = A6
mww 0xE000111C 0x00000007 # P1.7 = A7
mww 0xE0001028 0x00000007 # P0.10 = A8
mww 0xE000102C 0x00000007 # P0.11 = A9
mww 0xE0001030 0x00000007 # P0.12 = A10
mww 0xE0001034 0x00000007 # P0.13 = A11
mww 0xE0001038 0x00000007 # P0.14 = A12
mww 0xE000103C 0x00000007 # P0.15 = A13
mww 0xE0001048 0x00000007 # P0.18 = A14
mww 0xE000104C 0x00000007 # P0.19 = A15
mww 0xE0001050 0x00000007 # P0.20 = A16
mww 0xE0001054 0x00000007 # P0.21 = A17
mww 0xE0001058 0x00000007 # P0.22 = A18
mww 0xE000105C 0x00000007 # P0.23 = A19
mww 0xE0001238 0x00000007 # P2.14 = BLS0
mww 0xE000123C 0x00000007 # P2.15 = BLS1
mww 0xE0001300 0x00000007 # P3.0 = CS6
mww 0xE0001304 0x00000007 # P3.1 = CS7
mww 0xE0001130 0x00000007 # P1.12 = OE_N
mww 0xE0001134 0x00000007 # P1.13 = WE_N
mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1
mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0
mww 0x600000AC 0x00000005 # Bank6 WST1=5
mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1
mww 0x600000B0 0x00000006 # Bank6 WST2=6
mww 0x600000A8 0x00000002 # Bank6 IDCY=2
mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1
mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0
mww 0x600000C8 0x0000000A # Bank7 WST1=10
mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1
mww 0x600000CC 0x0000000C # Bank7 WST2=8
mww 0x600000C4 0x00000002 # Bank7 IDCY=2
if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME lpc2900
if { [info exists CPUTAPID ] } {
} else {
set _CPUTAPID 0x0596802B
if { [info exists HAS_ETB ] } {
} else {
# Set default (no ETB).
# Show a warning, because this should have been configured explicitely.
set HAS_ETB 0
# TODO warning?
if { [info exists ETBTAPID ] } {
} else {
set _ETBTAPID 0x1B900F0F
# TRST and SRST both exist, and can be controlled independently
reset_config trst_and_srst separate
# Define the _TARGETNAME
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
# Include the ETB tap controller if asked for.
# Has to be done manually for newer devices (not an "old" LPC2917/2919).
if { $HAS_ETB == 1 } {
# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
set HAS_ETB 0
# Add the ETB tap controller and the ARM9 core debug tap
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
# Configure ETM and ETB
etm config $_TARGETNAME 8 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
} else {
# Add the ARM9 core debug tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
arm7_9 dbgrq enable
arm7_9 dcc_downloads enable
# Flash bank configuration:
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
# Flash base address, total flash size, and number of sectors are all configured automatically.
flash bank lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
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