Commit 90465379 authored by oharboe's avatar oharboe
Browse files

David Brownell <david-b@pacbell.net> whitespace fixes.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1690 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 64e5467c
......@@ -113,13 +113,12 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = out_buf;
fields[1].in_value = NULL;
if (in)
{
u8 tmp[4];
......
......@@ -1287,7 +1287,7 @@ int arm7_9_full_context(target_t *target)
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
* SYS shares registers with User, so we don't touch SYS
*/
for(i = 0; i < 6; i++)
for (i = 0; i < 6; i++)
{
u32 mask = 0;
u32* reg_p[16];
......
......@@ -41,10 +41,10 @@
typedef struct arm7_9_common_s
{
u32 common_magic;
arm_jtag_t jtag_info;
reg_cache_t *eice_cache;
u32 arm_bkpt;
u16 thumb_bkpt;
int sw_breakpoints_added;
......@@ -58,32 +58,32 @@ typedef struct arm7_9_common_s
int dbgreq_adjust_pc;
int use_dbgrq;
int need_bypass_before_restart;
etm_context_t *etm_ctx;
int has_single_step;
int has_monitor_mode;
int has_vector_catch;
int debug_entry_from_reset;
struct working_area_s *dcc_working_area;
int fast_memory_access;
int dcc_downloads;
int (*examine_debug_reason)(target_t *target);
void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
void (*load_word_regs)(target_t *target, u32 mask);
void (*load_hword_reg)(target_t *target, int num);
void (*load_byte_reg)(target_t *target, int num);
......@@ -91,22 +91,22 @@ typedef struct arm7_9_common_s
void (*store_word_regs)(target_t *target, u32 mask);
void (*store_hword_reg)(target_t *target, int num);
void (*store_byte_reg)(target_t *target, int num);
void (*write_pc)(target_t *target, u32 pc);
void (*branch_resume)(target_t *target);
void (*branch_resume_thumb)(target_t *target);
void (*enable_single_step)(target_t *target, u32 next_pc);
void (*disable_single_step)(target_t *target);
void (*set_special_dbgrq)(target_t *target);
void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
void (*pre_restore_context)(target_t *target);
void (*post_restore_context)(target_t *target);
armv4_5_common_t armv4_5_common;
void *arch_info;
......
......@@ -115,13 +115,11 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = &breakpoint;
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = databus;
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{
......@@ -194,15 +192,12 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
u8 tmp[4];
fields[1].in_value = tmp;
jtag_add_dr_scan_now(2, fields, TAP_INVALID);
......@@ -286,14 +281,12 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
u8 tmp[4];
fields[1].in_value = tmp;
jtag_add_dr_scan_now(2, fields, TAP_INVALID);
......
......@@ -114,25 +114,21 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
......@@ -171,43 +167,23 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = value_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
......@@ -238,43 +214,23 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = cp15_opcode_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
......@@ -621,7 +577,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
arm920t_common_t *arm920t = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if((retval = target_halt(target)) != ERROR_OK)
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
......@@ -633,7 +589,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -676,7 +632,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
......@@ -814,7 +770,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -877,7 +833,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* read D RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -963,7 +919,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* read I RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1066,7 +1022,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1076,7 +1032,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read CP15 test state register */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1097,7 +1053,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1126,7 +1082,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1161,7 +1117,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1193,7 +1149,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1222,7 +1178,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1257,7 +1213,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -1347,7 +1303,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "couldn't access reg %i", address);
return ERROR_OK;
}
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......
......@@ -133,7 +133,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
buf_set_u32(address_buf, 0, 14, address);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
......@@ -151,20 +151,16 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
fields[1].out_value = &access;
fields[1].in_value = &access;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
/*TODO: add timeout*/
......@@ -177,7 +173,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
*value=le_to_h_u32(tmp);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -209,7 +205,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
......@@ -218,43 +214,23 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].in_value = &access;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, TAP_INVALID);
/*TODO: add timeout*/
do
......@@ -263,7 +239,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, TAP_INVALID);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -595,7 +571,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if((retval = target_halt(target)) != ERROR_OK)
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
......@@ -607,7 +583,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -812,7 +788,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
command_print(cmd_ctx, "couldn't access register");
return ERROR_OK;
}
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......
......@@ -128,41 +128,26 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = databus;
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_value = &debug_reason;
fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_value = instructionbus;
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -206,7 +191,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
buf_set_u32(&sysspeed_buf, 2, 1, 1);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
......@@ -217,20 +202,16 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].in_value = NULL;
if (in)
{
......@@ -249,7 +230,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
......@@ -273,7 +254,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
scan_field_t fields[3];
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
......@@ -285,19 +266,16 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[0].out_value = NULL;
u8 tmp[4];
fields[0].in_value = tmp;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_value = NULL;
jtag_add_dr_scan_now(3, fields, TAP_INVALID);
......@@ -307,7 +285,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
#ifdef _DEBUG_INSTRUCTION_EXECUTION_