Commit 8f518d35 authored by Marc Schink's avatar Marc Schink Committed by Tomas Vanek
Browse files

target/mips: Use 'bool' data type



Change-Id: Ifb114bfc062ed7c0ff6e4f37a1a6d546f5415344
Signed-off-by: default avatarMarc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4970


Tested-by: jenkins
Reviewed-by: default avatarAntonio Borneo <borneo.antonio@gmail.com>
parent b9eecd9c
......@@ -190,8 +190,8 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
......@@ -208,8 +208,8 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
reg_value = mips32->core_regs[num];
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32->core_cache->reg_list[num].valid = 1;
mips32->core_cache->reg_list[num].dirty = 0;
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
......@@ -227,8 +227,8 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
mips32->core_cache->reg_list[num].valid = 1;
mips32->core_cache->reg_list[num].dirty = 0;
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
......@@ -336,12 +336,12 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
reg_list[i].value = mips32_gdb_dummy_fp_value;
reg_list[i].valid = 1;
reg_list[i].valid = true;
reg_list[i].arch_info = NULL;
register_init_dummy(&reg_list[i]);
} else {
reg_list[i].value = calloc(1, 4);
reg_list[i].valid = 0;
reg_list[i].valid = false;
reg_list[i].type = &mips32_reg_type;
reg_list[i].arch_info = &arch_info[i];
......@@ -352,7 +352,7 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
LOG_ERROR("unable to allocate reg type list");
}
reg_list[i].dirty = 0;
reg_list[i].dirty = false;
reg_list[i].group = mips32_regs[i].group;
reg_list[i].number = i;
......@@ -532,8 +532,8 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
mips32->core_cache->reg_list[i].name, context[i]);
buf_set_u32(mips32->core_cache->reg_list[i].value,
0, 32, context[i]);
mips32->core_cache->reg_list[i].valid = 1;
mips32->core_cache->reg_list[i].dirty = 1;
mips32->core_cache->reg_list[i].valid = true;
mips32->core_cache->reg_list[i].dirty = true;
}
}
......
......@@ -458,8 +458,8 @@ static int mips_m4k_internal_restore(struct target *target, int current,
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
......@@ -552,8 +552,8 @@ static int mips_m4k_step(struct target *target, int current,
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
mips32->core_cache->reg_list[MIPS32_PC].valid = true;
}
/* the front-end may request us not to handle breakpoints */
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment