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Commit 8c290412 authored by ntfreak's avatar ntfreak
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- ST STM32x cortex support added 

- ST STM32x flash support added
- cleaned up armv7m and cortex-m3 support, removed luminary specific code
- cortex-m3 16bit read/write added (required for STM32x flash programming)

git-svn-id: svn://svn.berlios.de/openocd/trunk@177 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent ffb51c23
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src/flash/Makefile.am
View file @ 8c290412
INCLUDES = -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag -I$(top_srcdir)/src/target $(all_includes)
METASOURCES = AUTO
noinst_LIBRARIES = libflash.a
libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c stellaris.c str9xpec.c
noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h stellaris.h str9xpec.h
libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c \
stellaris.c str9xpec.c stm32x.c
noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
stellaris.h str9xpec.h stm32x.h
src/flash/flash.c
View file @ 8c290412
......@@ -57,6 +57,7 @@ extern flash_driver_t str7x_flash;
extern flash_driver_t str9x_flash;
extern flash_driver_t stellaris_flash;
extern flash_driver_t str9xpec_flash;
extern flash_driver_t stm32x_flash;
flash_driver_t *flash_drivers[] =
{
......@@ -67,6 +68,7 @@ flash_driver_t *flash_drivers[] =
&str9x_flash,
&stellaris_flash,
&str9xpec_flash,
&stm32x_flash,
NULL,
};
......
src/flash/stm32x.c 0 → 100644
View file @ 8c290412
This diff is collapsed.
src/flash/stm32x.h 0 → 100644
View file @ 8c290412
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef STM32X_H
#define STM32X_H
#include "flash.h"
#include "target.h"
typedef struct stm32x_flash_bank_s
{
struct target_s *target;
working_area_t *write_algorithm;
} stm32x_flash_bank_t;
/* stm32x register locations */
#define STM32_FLASH_ACR 0x40022000
#define STM32_FLASH_KEYR 0x40022004
#define STM32_FLASH_OPTKEYR 0x40022008
#define STM32_FLASH_SR 0x4002200C
#define STM32_FLASH_CR 0x40022010
#define STM32_FLASH_AR 0x40022014
#define STM32_FLASH_OBR 0x4002201C
#define STM32_FLASH_WRPR 0x40022020
/* option byte location */
#define STM32_OB_ADR 0x1FFFF800
/* FLASH_CR register bits */
#define FLASH_PG (1<<0)
#define FLASH_PER (1<<1)
#define FLASH_MER (1<<2)
#define FLASH_OPTPG (1<<4)
#define FLASH_OPTER (1<<5)
#define FLASH_STRT (1<<6)
#define FLASH_LOCK (1<<7)
#define FLASH_OPTWRE (1<<9)
/* FLASH_SR regsiter bits */
#define FLASH_BSY (1<<0)
#define FLASH_PGERR (1<<2)
#define FLASH_WRPRTERR (1<<4)
#define FLASH_EOP (1<<5)
/* STM32_FLASH_OBR bit definitions (reading) */
#define OPT_ERROR 0
#define OPT_READOUT 1
#define OPT_RDWDGSW 2
#define OPT_RDRSTSTOP 3
#define OPT_RDRSTSTDBY 4
/* register unlock keys */
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
typedef struct stm32x_mem_layout_s {
u32 sector_start;
u32 sector_size;
} stm32x_mem_layout_t;
#endif /* STM32X_H */
src/target/arm_disassembler.c
View file @ 8c290412
......@@ -346,7 +346,7 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
if (offset_12)
snprintf(offset, 32, ", #%s0x%x", (U) ? "" : "-", offset_12);
else
snprintf(offset, 32, "");
snprintf(offset, 32, "%s", "");
instruction->info.load_store.offset_mode = 0;
instruction->info.load_store.offset.offset = offset_12;
......
src/target/armv7m.c
View file @ 8c290412
......@@ -129,8 +129,10 @@ enum armv7m_runcontext armv7m_get_context(target_t *target)
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
if (armv7m->process_context == armv7m->core_cache) return ARMV7M_PROCESS_CONTEXT;
if (armv7m->debug_context == armv7m->core_cache) return ARMV7M_DEBUG_CONTEXT;
if (armv7m->process_context == armv7m->core_cache)
return ARMV7M_PROCESS_CONTEXT;
if (armv7m->debug_context == armv7m->core_cache)
return ARMV7M_DEBUG_CONTEXT;
ERROR("Invalid runcontext");
exit(-1);
......@@ -177,9 +179,11 @@ int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
char enamebuf[32];
char *armv7m_exception_string(int number)
{
if ((number<0)|(number>511)) return "Invalid exception";
if (number<16) return armv7m_exception_strings[number];
sprintf(enamebuf,"External Interrupt(%i)",number-16);
if ((number < 0) | (number > 511))
return "Invalid exception";
if (number < 16)
return armv7m_exception_strings[number];
sprintf(enamebuf, "External Interrupt(%i)", number - 16);
return enamebuf;
}
......@@ -252,26 +256,22 @@ int armv7m_write_core_reg(struct target_s *target, int num)
if ((num < 0) || (num >= ARMV7NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
if (retval != ERROR_OK)
{
ERROR("JTAG failure");
armv7m->core_cache->reg_list[num].dirty=1;
return ERROR_JTAG_DEVICE_ERROR;
ERROR("JTAG failure");
armv7m->core_cache->reg_list[num].dirty=1;
return ERROR_JTAG_DEVICE_ERROR;
}
DEBUG("write core reg %i value 0x%x",num ,reg_value);
armv7m->core_cache->reg_list[num].valid=1;
armv7m->core_cache->reg_list[num].dirty=0;
return ERROR_OK;
}
int armv7m_invalidate_core_regs(target_t *target)
{
/* get pointers to arch-specific information */
......@@ -287,14 +287,12 @@ int armv7m_invalidate_core_regs(target_t *target)
return ERROR_OK;
}
int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
int i;
if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
......@@ -306,7 +304,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
/* TODOLATER correct list of registers, names ? */
for (i = 0; i < *reg_list_size; i++)
{
if (i<ARMV7NUMCOREREGS)
if (i < ARMV7NUMCOREREGS)
(*reg_list)[i] = &armv7m->process_context->reg_list[i];
//(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
else
......@@ -382,7 +380,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
armv7m_set_core_reg(reg, reg_params[i].value);
}
/* ARMV7M always runs in Tumb state */
/* ARMV7M always runs in Thumb state */
exit_breakpoint_size = 2;
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
{
......@@ -415,7 +413,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
}
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
DEBUG("failed algoritm halted at 0x%x ",pc);
DEBUG("failed algoritm halted at 0x%x ", pc);
retval = ERROR_TARGET_TIMEOUT;
}
}
......@@ -450,7 +448,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
exit(-1);
}
armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
armv7m_core_reg_t *armv7m_core_reg = reg->arch_info;
//armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &regvalue);
//buf_set_u32(reg_params[i].value, 0, 32, regvalue);
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
......@@ -464,11 +462,9 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
// armv7m->core_cache->reg_list[i].dirty = 1;
//}
// ????armv7m->core_state = core_state;
// ????armv7m->core_mode = core_mode;
return retval;
}
......@@ -478,20 +474,19 @@ int armv7m_arch_state(struct target_s *target, char *buf, int buf_size)
armv7m_common_t *armv7m = target->arch_info;
snprintf(buf, buf_size,
"target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
armv7m_state_strings[armv7m->core_state],
target_debug_reason_strings[target->debug_reason],
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
"target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
armv7m_state_strings[armv7m->core_state],
target_debug_reason_strings[target->debug_reason],
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
return ERROR_OK;
}
reg_cache_t *armv7m_build_reg_cache(target_t *target)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
arm_jtag_t *jtag_info = &armv7m->jtag_info;
......@@ -560,16 +555,13 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target)
int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
armv7m_build_reg_cache(target);
return ERROR_OK;
}
int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
{
/* register arch-specific functions */
target->arch_info = armv7m;
......@@ -580,11 +572,9 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
return ERROR_OK;
}
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
return ERROR_OK;
}
src/target/armv7m.h
View file @ 8c290412
......@@ -26,7 +26,6 @@
#include "target.h"
#include "arm_jtag.h"
enum armv7m_mode
{
ARMV7M_MODE_HANDLER = 0,
......@@ -56,17 +55,18 @@ enum armv7m_runcontext
};
extern char* armv7m_state_strings[];
extern char* armv7m_exception_strings[];
//#define ARMV7NUMCOREREGS 23
extern char *armv7m_exception_string(int number);
/* offsets into armv7m core register cache */
enum
{
ARMV7M_PC = 15,
ARMV7M_xPSR = 16,
ARMV7M_MSP ,
ARMV7M_PSP ,
ARMV7M_PRIMASK ,
ARMV7M_MSP,
ARMV7M_PSP,
ARMV7M_PRIMASK,
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,
ARMV7M_CONTROL,
......@@ -163,8 +163,9 @@ extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem
extern int armv7m_invalidate_core_regs(target_t *target);
extern enum armv7m_runcontext armv7m_get_context(target_t *target);
extern int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx);
extern enum armv7m_runcontext armv7m_get_context(target_t *target);
/* Thumb mode instructions
*/
......
src/target/breakpoints.c
View file @ 8c290412
......@@ -71,13 +71,15 @@ int breakpoint_add(target_t *target, u32 address, u32 length, enum breakpoint_ty
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
INFO("can't add %s breakpoint, resource not available", breakpoint_type_strings[(*breakpoint_p)->type]);
free (*breakpoint_p);
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
return retval;
break;
case ERROR_TARGET_NOT_HALTED:
INFO("can't add breakpoint while target is running");
free (*breakpoint_p);
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
return retval;
break;
......
src/target/cortex_m3.c
View file @ 8c290412
This diff is collapsed.
src/target/cortex_m3.h
View file @ 8c290412
......@@ -40,7 +40,6 @@ extern char* cortex_m3_state_strings[];
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
#define DCRSR_WnR (1<<16)
#define DWT_CTRL 0xE0001000
......@@ -107,7 +106,6 @@ extern char* cortex_m3_state_strings[];
#define DFSR_DWTTRAP 4
#define DFSR_VCATCH 8
#define FPCR_CODE 0
#define FPCR_LITERAL 1
#define FPCR_REPLACE_REMAP (0<<30)
......@@ -149,16 +147,16 @@ typedef struct cortex_m3_common_s
int fp_num_code;
int fp_code_available;
int auto_bp_type;
cortex_m3_fp_comparator_t * fp_comparator_list;
cortex_m3_fp_comparator_t *fp_comparator_list;
/* DWT */
int dwt_num_comp;
int dwt_comp_available;
cortex_m3_dwt_comparator_t * dwt_comparator_list;
cortex_m3_dwt_comparator_t *dwt_comparator_list;
/* Interrupts */
int intlinesnum;
u32 * intsetenable;
u32 *intsetenable;
/*
u32 arm_bkpt;
......@@ -189,7 +187,6 @@ typedef struct cortex_m3_common_s
void *arch_info;
} cortex_m3_common_t;
extern void cortex_m3_build_reg_cache(target_t *target);
enum target_state cortex_m3_poll(target_t *target);
......
src/target/cortex_swjdp.c
View file @ 8c290412
This diff is collapsed.
src/target/cortex_swjdp.h
View file @ 8c290412
......@@ -44,8 +44,6 @@
#define CSYSPWRUPREQ (1<<30)
#define CSYSPWRUPACK (1<<31)
#define AHBAP_CSW 0x00
#define AHBAP_TAR 0x04
#define AHBAP_DRW 0x0C
......@@ -56,7 +54,6 @@
#define AHBAP_DBGROMA 0xF8
#define AHBAP_IDR 0xFC
#define CSW_8BIT 0
#define CSW_16BIT 1
#define CSW_32BIT 2
......@@ -65,17 +62,17 @@
#define CSW_ADDRINC_OFF 0
#define CSW_ADDRINC_SINGLE (1<<4)
#define CSW_ADDRINC_PACKED (2<<4)
#define CSW_HPROT (1<<25)
#define CSW_HPROT (1<<25)
#define CSW_MASTER_DEBUG (1<<29)
#define CSW_DBGSWENABLE (1<<31)
#define TRANS_MODE_NONE 0
#define CSW_DBGSWENABLE (1<<31)
/* transaction mode */
#define TRANS_MODE_NONE 0
/* Transaction waits for previous to complete */
#define TRANS_MODE_ATOMIC 1
/* Freerunning transactions with delays and overrun checking */
#define TRANS_MODE_COMPOSITE 2
typedef struct swjdp_reg_s
{
int addr;
......@@ -96,7 +93,7 @@ typedef struct swjdp_common_s
u8 trans_mode;
u8 trans_rw;
u8 ack;
u32 * trans_value;
u32 *trans_value;
} swjdp_common_t;
/* Internal functions used in the module, partial transactions, use with caution */
......@@ -112,7 +109,6 @@ extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
/* External interface, complete atomic operations */
/* Host endian word transfer of single memory and system registers */
extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
......@@ -124,6 +120,11 @@ extern int ahbap_write_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u
extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
extern int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
extern int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
/* Initialisation of the debug system, power domains and registers */
extern int ahbap_debugport_init(swjdp_common_t *swjdp);
......
src/target/target.c
View file @ 8c290412
......@@ -653,6 +653,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
{
if ((retval = target->type->write_memory(target, address, 1, size, buffer)) != ERROR_OK)
return retval;
return ERROR_OK;
}
/* handle unaligned head bytes */
......@@ -711,6 +712,7 @@ int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffe
{
if ((retval = target->type->read_memory(target, address, 1, size, buffer)) != ERROR_OK)
return retval;
return ERROR_OK;
}
/* handle unaligned head bytes */
......
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