Commit 86173cdb authored by zwelch's avatar zwelch
Browse files

Transform 'u8' to 'uint8_t' in src/target

- Replace '\([^_]\)u8' with '\1uint8_t'.
- Replace '^u8' with 'uint8_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2274 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 8f9f5c18
......@@ -33,7 +33,7 @@ typedef struct mem_param_s
{
u32 address;
u32 size;
u8 *value;
uint8_t *value;
enum param_direction direction;
} mem_param_t;
......@@ -41,7 +41,7 @@ typedef struct reg_param_s
{
char *reg_name;
u32 size;
u8 *value;
uint8_t *value;
enum param_direction direction;
} reg_param_t;
......
......@@ -288,14 +288,14 @@ enum arm11_regcache_ids
#define ARM11_GDB_REGISTER_COUNT 26
u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t arm11_gdb_dummy_fps_reg =
{
......@@ -630,8 +630,8 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
scan_field_t chain5_fields[3];
u8 Ready = 0; /* ignored */
u8 Valid = 0; /* ignored */
uint8_t Ready = 0; /* ignored */
uint8_t Valid = 0; /* ignored */
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
......@@ -717,7 +717,7 @@ int arm11_arch_state(struct target_s *target)
}
/* target request support */
int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer)
{
FNC_INFO_NOTIMPLEMENTED;
......@@ -1090,7 +1090,7 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
/** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
......@@ -1173,7 +1173,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
return ERROR_OK;
}
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
FNC_INFO;
......@@ -1285,7 +1285,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer)
{
FNC_INFO;
......@@ -1395,11 +1395,11 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
// Save regs
for (size_t i = 0; i < 16; i++)
{
context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
}
cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
cpsr = buf_get_u32((uint8_t*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
LOG_DEBUG("Save CPSR: 0x%x", cpsr);
for (int i = 0; i < num_mem_params; i++)
......@@ -1521,10 +1521,10 @@ restore:
{
LOG_DEBUG("restoring register %s with value 0x%8.8x",
arm11->reg_list[i].name, context[i]);
arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
}
LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
// arm11->core_state = core_state;
// arm11->core_mode = core_mode;
......@@ -1668,7 +1668,7 @@ int arm11_get_reg(reg_t *reg)
}
/** Change a value in the register cache */
int arm11_set_reg(reg_t *reg, u8 *buf)
int arm11_set_reg(reg_t *reg, uint8_t *buf)
{
FNC_INFO;
......@@ -1730,7 +1730,7 @@ int arm11_build_reg_cache(target_t *target)
r->name = rd->name;
r->size = 32;
r->value = (u8 *)(arm11->reg_values + i);
r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
r->bitfield_desc = NULL;
......
......@@ -66,7 +66,7 @@ do { \
typedef struct arm11_register_history_s
{
u32 value;
u8 valid;
uint8_t valid;
}arm11_register_history_t;
enum arm11_debug_version
......@@ -86,7 +86,7 @@ typedef struct arm11_common_s
u32 device_id; /**< IDCODE readout */
u32 didr; /**< DIDR readout (debug capabilities) */
u8 implementor; /**< DIDR Implementor readout */
uint8_t implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
......@@ -191,7 +191,7 @@ int arm11_poll(struct target_s *target);
int arm11_arch_state(struct target_s *target);
/* target request support */
int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
int arm11_target_request_data(struct target_s *target, u32 size, uint8_t *buffer);
/* target execution control */
int arm11_halt(struct target_s *target);
......@@ -211,11 +211,11 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, uint8_t *buffer);
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
......@@ -237,7 +237,7 @@ int arm11_quit(void);
/* helpers */
int arm11_build_reg_cache(target_t *target);
int arm11_set_reg(reg_t *reg, u8 *buf);
int arm11_set_reg(reg_t *reg, uint8_t *buf);
int arm11_get_reg(reg_t *reg);
void arm11_record_register_history(arm11_common_t * arm11);
......@@ -246,9 +246,9 @@ void arm11_dump_reg_changes(arm11_common_t * arm11);
/* internals */
void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state);
int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
......@@ -275,7 +275,7 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state
typedef struct arm11_sc7_action_s
{
bool write; /**< Access mode: true for write, false for read. */
u8 address; /**< Register address mode. Use enum #arm11_sc7 */
uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
u32 value; /**< If write then set this to value to be written.
In read mode this receives the read value when the
function returns. */
......
......@@ -97,7 +97,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
{
jtag_tap_t *tap;
tap = arm11->target->tap;
......@@ -122,10 +122,10 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
* arm11_add_debug_SCAN_N().
*
*/
static void arm11_in_handler_SCAN_N(u8 *in_value)
static void arm11_in_handler_SCAN_N(uint8_t *in_value)
{
/** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
u8 v = *in_value & 0x1F;
uint8_t v = *in_value & 0x1F;
if (v != 0x10)
{
......@@ -160,7 +160,7 @@ static void arm11_in_handler_SCAN_N(u8 *in_value)
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
......@@ -168,7 +168,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
scan_field_t field;
u8 tmp[1];
uint8_t tmp[1];
arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
......@@ -195,7 +195,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
......@@ -374,7 +374,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
while (1)
{
u8 flag;
uint8_t flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
......@@ -426,8 +426,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data,
scan_field_t chain5_fields[3];
u32 Data;
u8 Ready;
u8 nRetry;
uint8_t Ready;
uint8_t nRetry;
arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
......@@ -516,8 +516,8 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 *
arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
u8 Readies[count + 1];
u8 * ReadyPos = Readies;
uint8_t Readies[count + 1];
uint8_t * ReadyPos = Readies;
while (count--)
{
......@@ -603,8 +603,8 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat
scan_field_t chain5_fields[3];
u32 Data;
u8 Ready;
u8 nRetry;
uint8_t Ready;
uint8_t nRetry;
arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
......@@ -685,12 +685,12 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c
scan_field_t chain7_fields[3];
u8 nRW;
uint8_t nRW;
u32 DataOut;
u8 AddressOut;
u8 Ready;
uint8_t AddressOut;
uint8_t Ready;
u32 DataIn;
u8 AddressIn;
uint8_t AddressIn;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
......
......@@ -43,8 +43,8 @@ int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm720t_quit(void);
int arm720t_arch_state(struct target_s *target);
int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
target_type_t arm720t_target =
......@@ -91,8 +91,8 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
scan_field_t fields[2];
u8 out_buf[4];
u8 instruction_buf = instruction;
uint8_t out_buf[4];
uint8_t instruction_buf = instruction;
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
......@@ -118,9 +118,9 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
if (in)
{
fields[1].in_value = (u8 *)in;
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_callback(arm7flip32, (u8 *)in);
jtag_add_callback(arm7flip32, (uint8_t *)in);
} else
{
jtag_add_dr_scan(2, fields, jtag_get_end_state());
......@@ -329,7 +329,7 @@ int arm720t_arch_state(struct target_s *target)
return ERROR_OK;
}
int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
......@@ -349,7 +349,7 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
return retval;
}
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
int retval;
......
......@@ -373,7 +373,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
{
return retval;
}
......@@ -387,7 +387,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
{
return retval;
}
......@@ -739,7 +739,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
static int set=0;
static u8 check_value[4], check_mask[4];
static uint8_t check_value[4], check_mask[4];
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
......@@ -781,7 +781,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
* @param buffer Pointer to the buffer that will hold the data
* @return The result of receiving data from the Embedded ICE unit
*/
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
......@@ -2208,7 +2208,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
return jtag_execute_queue();
}
int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
......@@ -2384,7 +2384,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
return ERROR_OK;
}
int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
......@@ -2568,7 +2568,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
}
static int dcc_count;
static u8 *dcc_buffer;
static uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
{
......@@ -2581,7 +2581,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
int little=target->endianness==TARGET_LITTLE_ENDIAN;
int count=dcc_count;
u8 *buffer=dcc_buffer;
uint8_t *buffer=dcc_buffer;
if (count>2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
......@@ -2590,7 +2590,7 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
buffer+=4;
embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
uint8_t reg_addr = ice_reg->addr & 0x1f;
jtag_tap_t *tap;
tap = ice_reg->jtag_info->tap;
......@@ -2623,7 +2623,7 @@ static const u32 dcc_code[] =
int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
......@@ -2636,7 +2636,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area)
{
u8 dcc_code_buf[6 * 4];
uint8_t dcc_code_buf[6 * 4];
/* make sure we have a working area */
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
......
......@@ -80,7 +80,7 @@ typedef struct arm7_9_common_s
void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
void (*load_word_regs)(target_t *target, u32 mask);
......@@ -115,7 +115,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx);
int arm7_9_poll(target_t *target);
int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer);
int arm7_9_setup(target_t *target);
int arm7_9_assert_reset(target_t *target);
......@@ -131,9 +131,9 @@ int arm7_9_restore_context(target_t *target);
int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer);
int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
......
......@@ -95,8 +95,8 @@ int arm7tdmi_examine_debug_reason(target_t *target)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
scan_field_t fields[2];
u8 databus[4];
u8 breakpoint;
uint8_t databus[4];
uint8_t breakpoint;
jtag_set_end_state(TAP_DRPAUSE);
......@@ -185,11 +185,11 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = (u8 *)in;
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_callback(arm7flip32, (u8 *)in);
jtag_add_callback(arm7flip32, (uint8_t *)in);
jtag_add_runtest(0, jtag_get_end_state());
......@@ -214,7 +214,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
return ERROR_OK;
}
void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
{
u32 readback=le_to_h_u32(tmp);
if (flip)
......@@ -224,30 +224,30 @@ void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
case 4:
if (be)
{
h_u32_to_be(((u8*)in), readback);
h_u32_to_be(((uint8_t*)in), readback);
} else
{
h_u32_to_le(((u8*)in), readback);
h_u32_to_le(((uint8_t*)in), readback);
}
break;
case 2:
if (be)
{
h_u16_to_be(((u8*)in), readback & 0xffff);
h_u16_to_be(((uint8_t*)in), readback & 0xffff);
} else
{
h_u16_to_le(((u8*)in), readback & 0xffff);
h_u16_to_le(((uint8_t*)in), readback & 0xffff);
}
break;
case 1:
*((u8 *)in)= readback & 0xff;
*((uint8_t *)in)= readback & 0xff;
break;
}
}
static int arm7endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
static int arm7endianness(uint8_t *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
{
arm_endianness((u8 *)captured, in, (int)size, (int)be, 1);
arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1);
return ERROR_OK;
}
......@@ -397,7 +397,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer;
uint8_t *buf_u8 = buffer;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
......@@ -481,7 +481,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
......
......@@ -48,8 +48,8 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm920t_quit(void);
int arm920t_arch_state(struct target_s *target);
int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
int arm920t_soft_reset_halt(struct target_s *target);
#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
......@@ -99,9 +99,9 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
scan_field_t fields[4];
u8 access_type_buf = 1;
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0;
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
......@@ -129,11 +129,11 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
jtag_add_dr_scan(4, fields, jtag_get_end_state());
fields[1].in_value = (u8 *)value;
fields[1].in_value = (uint8_t *)value;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
......@@ -149,10 +149,10 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
scan_field_t fields[4];
u8 access_type_buf = 1;
u8 reg_addr_buf = reg_addr & 0x3f;