Commit 815c3b35 authored by oharboe's avatar oharboe
Browse files

- "flash write_binary" is now "flash write_bank" to clarify the focus of the
 command and reduce confusion with "flash write_image".
- retired deprecated "flash erase" & "flash write".
- added flash_driver_protect/write/erase() that are wafer thin frontend
 functions to low level driver functions. They implement checks
 that were inconsistently handled by the drivers, e.g. check for
 target halted was done in a spotty fashion.
- use return ERROR_COMMAND_SYNTAX_ERROR to print out
 syntax of command instead of having lots of inlined replicas of
 the command line syntax(some of which were wrong).
- use logging instead of dubious translation of error values to
 human understandable explanations of why things failed.
 The lower levels log the precise reason and the higher
 levels can ammend context as the error propagates up
 the call stack.
- simplified flash API slightly with logging instead of
 allocating and returning information that the caller then
 has to translate into print statements.



git-svn-id: svn://svn.berlios.de/openocd/trunk@337 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent d8456e48
/***************************************************************************
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
/***************************************************************************
There are some things to notice
* AT91SAM7S64 is tested
* All AT91SAM7Sxx and AT91SAM7Xxx should work but is not tested
* All parameters are identified from onchip configuartion registers
*
* The flash controller handles erases automatically on a page (128/265 byte) basis
* Only an EraseAll command is supported by the controller
* Partial erases can be implemented in software by writing one 0xFFFFFFFF word to
* some location in every page in the region to be erased
*
* Lock regions (sectors) are 32 or 64 pages
*
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "replacements.h"
#include "at91sam7.h"
#include "flash.h"
#include "target.h"
#include "log.h"
#include "binarybuffer.h"
#include "types.h"
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
int at91sam7_register_commands(struct command_context_s *cmd_ctx);
int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
int at91sam7_probe(struct flash_bank_s *bank);
int at91sam7_auto_probe(struct flash_bank_s *bank);
int at91sam7_erase_check(struct flash_bank_s *bank);
int at91sam7_protect_check(struct flash_bank_s *bank);
int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane);
void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);
u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);
int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen);
int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
{
.name = "at91sam7",
.register_commands = at91sam7_register_commands,
.flash_bank_command = at91sam7_flash_bank_command,
.erase = at91sam7_erase,
.protect = at91sam7_protect,
.write = at91sam7_write,
.probe = at91sam7_probe,
.auto_probe = at91sam7_auto_probe,
.erase_check = at91sam7_erase_check,
.protect_check = at91sam7_protect_check,
.info = at91sam7_info
};
u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
long NVPSIZ[16] = {
0,
0x2000, /* 8K */
0x4000, /* 16K */
0x8000, /* 32K */
-1,
0x10000, /* 64K */
-1,
0x20000, /* 128K */
-1,
0x40000, /* 256K */
0x80000, /* 512K */
-1,
0x100000, /* 1024K */
-1,
0x200000, /* 2048K */
-1
};
long SRAMSIZ[16] = {
-1,
0x0400, /* 1K */
0x0800, /* 2K */
-1,
0x1c000, /* 112K */
0x1000, /* 4K */
0x14000, /* 80K */
0x28000, /* 160K */
0x2000, /* 8K */
0x4000, /* 16K */
0x8000, /* 32K */
0x10000, /* 64K */
0x20000, /* 128K */
0x40000, /* 256K */
0x18000, /* 96K */
0x80000, /* 512K */
};
int at91sam7_register_commands(struct command_context_s *cmd_ctx)
{
command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
"at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");
return ERROR_OK;
}
u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane)
{
target_t *target = bank->target;
u32 fsr;
target_read_u32(target, MC_FSR[flashplane], &fsr);
return fsr;
}
/** Read clock configuration and set at91sam7_info->usec_clocks*/
void at91sam7_read_clock_info(flash_bank_t *bank)
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 mckr, mcfr, pllr;
unsigned long tmp = 0, mainfreq;
int flashplane;
/* Read main clock freqency register */
target_read_u32(target, CKGR_MCFR, &mcfr);
/* Read master clock register */
target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7_info->mck_valid = 0;
switch (mckr & PMC_MCKR_CSS)
{
case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
tmp = mainfreq;
break;
case 1: /* Main Clock */
if (mcfr & CKGR_MCFR_MAINRDY)
{
at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
tmp = mainfreq;
}
break;
case 2: /* Reserved */
break;
case 3: /* PLL Clock */
if (mcfr & CKGR_MCFR_MAINRDY)
{
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
break; /* 0 Hz */
at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
/* Integer arithmetic should have sufficient precision
as long as PLL is properly configured. */
tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *
(((pllr & CKGR_PLLR_MUL) >> 16) + 1);
}
break;
}
/* Prescaler adjust */
if (((mckr & PMC_MCKR_PRES) >> 2) == 7)
at91sam7_info->mck_valid = 0;
else
at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
/* Forget old flash timing */
for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++)
{
at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE);
}
}
/* Setup the timimg registers for nvbits or normal flash */
void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)
{
u32 fmr, fmcn = 0, fws = 0;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
if (mode && (mode != at91sam7_info->flashmode[flashplane]))
{
/* Always round up (ceil) */
if (mode==FMR_TIMING_NVBITS)
{
if (at91sam7_info->cidr_arch == 0x60)
{
/* AT91SAM7A3 uses master clocks in 100 ns */
fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
}
else
{
/* master clocks in 1uS for ARCH 0x7 types */
fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
}
}
else if (mode==FMR_TIMING_FLASH)
/* main clocks in 1.5uS */
fmcn = (at91sam7_info->mck_freq/666666ul)+1;
/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
if (at91sam7_info->mck_freq <= 33333ul)
fmcn = 0;
/* Only allow fws=0 if clock frequency is < 30 MHz. */
if (at91sam7_info->mck_freq > 30000000ul)
fws = 1;
DEBUG("fmcn[%i]: %i", flashplane, fmcn);
fmr = fmcn << 16 | fws << 8;
target_write_u32(target, MC_FMR[flashplane], fmr);
}
at91sam7_info->flashmode[flashplane] = mode;
}
u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)
{
u32 status;
while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
{
DEBUG("status[%i]: 0x%x", flashplane, status);
usleep(1000);
}
DEBUG("status[%i]: 0x%x", flashplane, status);
if (status & 0x0C)
{
ERROR("status register: 0x%x", status);
if (status & 0x4)
ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8)
ERROR("Invalid command and/or bad keyword, Operation Abort");
if (status & 0x10)
ERROR("Security Bit Set, Operation Abort");
}
return status;
}
/* Send one command to the AT91SAM flash controller */
int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen)
{
u32 fcr;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
target_write_u32(target, MC_FCR[flashplane], fcr);
DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);
if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
{
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}
if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}
/* Read device id register, main clock frequency register and fill in driver info structure */
int at91sam7_read_part_info(struct flash_bank_s *bank)
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 cidr, status;
int sectornum;
if (bank->target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
/* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr);
if (cidr == 0)
{
WARNING("Cannot identify target as an AT91SAM");
return ERROR_FLASH_OPERATION_FAILED;
}
at91sam7_info->cidr = cidr;
at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
at91sam7_info->cidr_version = cidr&0x001F;
bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz];
at91sam7_info->target_name = "Unknown";
/* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */
if (NVPSIZ[at91sam7_info->cidr_nvpsiz]<0x80000) /* Flash size less than 512K, one flash plane */
{
bank->num_sectors = 1;
bank->sectors = malloc(sizeof(flash_sector_t));
bank->sectors[0].offset = 0;
bank->sectors[0].size = bank->size;
bank->sectors[0].is_erased = -1;
bank->sectors[0].is_protected = -1;
}
else /* Flash size 512K or larger, several flash planes */
{
bank->num_sectors = NVPSIZ[at91sam7_info->cidr_nvpsiz]/0x40000;
bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t));
for (sectornum=0; sectornum<bank->num_sectors; sectornum++)
{
bank->sectors[sectornum].offset = sectornum*0x40000;
bank->sectors[sectornum].size = 0x40000;
bank->sectors[sectornum].is_erased = -1;
bank->sectors[sectornum].is_protected = -1;
}
}
DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
/* Read main and master clock freqency register */
at91sam7_read_clock_info(bank);
at91sam7_info->num_planes = 1;
status = at91sam7_get_flash_status(bank, 0);
at91sam7_info->securitybit = (status>>4)&0x01;
at91sam7_protect_check(bank); /* TODO Check the protect check */
if (at91sam7_info->cidr_arch == 0x70 )
{
at91sam7_info->num_nvmbits = 2;
at91sam7_info->nvmbits = (status>>8)&0x03;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7S512 */
{
at91sam7_info->target_name = "AT91SAM7S512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 2*16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 2*16*64;
}
if (bank->size==0x40000) /* AT91SAM7S256 */
{
at91sam7_info->target_name = "AT91SAM7S256";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 16*64;
}
if (bank->size==0x20000) /* AT91SAM7S128 */
{
at91sam7_info->target_name = "AT91SAM7S128";
at91sam7_info->num_lockbits = 8;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 8*64;
}
if (bank->size==0x10000) /* AT91SAM7S64 */
{
at91sam7_info->target_name = "AT91SAM7S64";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 128;
at91sam7_info->pages_in_lockregion = 32;
at91sam7_info->num_pages = 16*32;
}
if (bank->size==0x08000) /* AT91SAM7S321/32 */
{
at91sam7_info->target_name = "AT91SAM7S321/32";
at91sam7_info->num_lockbits = 8;
at91sam7_info->pagesize = 128;
at91sam7_info->pages_in_lockregion = 32;
at91sam7_info->num_pages = 8*32;
}
return ERROR_OK;
}
if (at91sam7_info->cidr_arch == 0x71 )
{
at91sam7_info->num_nvmbits = 3;
at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7XC512 */
{
at91sam7_info->target_name = "AT91SAM7XC512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 2*16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 2*16*64;
}
if (bank->size==0x40000) /* AT91SAM7XC256 */
{
at91sam7_info->target_name = "AT91SAM7XC256";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 16*64;
}
if (bank->size==0x20000) /* AT91SAM7XC128 */
{
at91sam7_info->target_name = "AT91SAM7XC128";
at91sam7_info->num_lockbits = 8;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 8*64;
}
return ERROR_OK;
}
if (at91sam7_info->cidr_arch == 0x72 )
{
at91sam7_info->num_nvmbits = 3;
at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7SE512 */
{
at91sam7_info->target_name = "AT91SAM7SE512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 32;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 32*64;
}
if (bank->size==0x40000)
{
at91sam7_info->target_name = "AT91SAM7SE256";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 16*64;
}
if (bank->size==0x08000)
{
at91sam7_info->target_name = "AT91SAM7SE32";
at91sam7_info->num_lockbits = 8;
at91sam7_info->pagesize = 128;
at91sam7_info->pages_in_lockregion = 32;
at91sam7_info->num_pages = 8*32;
}
return ERROR_OK;
}
if (at91sam7_info->cidr_arch == 0x75 )
{
at91sam7_info->num_nvmbits = 3;
at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7X512 */
{
at91sam7_info->target_name = "AT91SAM7X512";
at91sam7_info->num_planes = 2;
if (at91sam7_info->num_planes != bank->num_sectors)
WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;
at91sam7_info->num_lockbits = 32;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 2*16*64;
DEBUG("Support for AT91SAM7X512 is experimental in this version!");
}
if (bank->size==0x40000) /* AT91SAM7X256 */
{
at91sam7_info->target_name = "AT91SAM7X256";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 16*64;
}
if (bank->size==0x20000) /* AT91SAM7X128 */
{
at91sam7_info->target_name = "AT91SAM7X128";
at91sam7_info->num_lockbits = 8;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 64;
at91sam7_info->num_pages = 8*64;
}
return ERROR_OK;
}
if (at91sam7_info->cidr_arch == 0x60 )
{
at91sam7_info->num_nvmbits = 3;
at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000;
bank->bus_width = 4;
if (bank->size == 0x40000) /* AT91SAM7A3 */
{
at91sam7_info->target_name = "AT91SAM7A3";
at91sam7_info->num_lockbits = 16;
at91sam7_info->pagesize = 256;
at91sam7_info->pages_in_lockregion = 16;
at91sam7_info->num_pages = 16*64;
}
return ERROR_OK;
}
WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
return ERROR_OK;
}
int at91sam7_erase_check(struct flash_bank_s *bank)
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
if (!at91sam7_info->working_area_size)
{
}
else
{
}
return ERROR_OK;
}
int at91sam7_protect_check(struct flash_bank_s *bank)
{
u32 status;
int flashplane;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
if (at91sam7_info->cidr == 0)
{
at91sam7_read_part_info(bank);
}
if (at91sam7_info->cidr == 0)
{
WARNING("Cannot identify target as an AT91SAM");
return ERROR_FLASH_OPERATION_FAILED;
}
for (flashplane=0;flashplane<at91sam7_info->num_planes;flashplane++)
{
status = at91sam7_get_flash_status(bank, flashplane);
at91sam7_info->lockbits[flashplane] = (status >> 16);
}
return ERROR_OK;
}
/* flash_bank at91sam7 0 0 0 0 <target#>
*/
int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
at91sam7_flash_bank_t *at91sam7_info;
int i;