Commit 74d09617 authored by Zachary T Welch's avatar Zachary T Welch
Browse files

reg_cache_t -> struct reg_cache

Remove misleading typedef and redundant suffix from struct reg_cache.
parent de3fb2f3
......@@ -1933,7 +1933,7 @@ static int arm11_build_reg_cache(target_t *target)
{
struct arm11_common *arm11 = target->arch_info;
NEW(reg_cache_t, cache, 1);
NEW(struct reg_cache, cache, 1);
NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
......@@ -1951,7 +1951,7 @@ static int arm11_build_reg_cache(target_t *target)
cache->reg_list = reg_list;
cache->num_regs = ARM11_REGCACHE_COUNT;
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
(*cache_p) = cache;
arm11->core_cache = cache;
......
......@@ -116,7 +116,7 @@ struct arm11_common
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA
reg_cache_t *core_cache;
struct reg_cache *core_cache;
};
......
......@@ -43,7 +43,7 @@ struct arm7_9_common
uint32_t common_magic;
struct arm_jtag jtag_info; /**< JTAG information for target */
reg_cache_t *eice_cache; /**< Embedded ICE register cache */
struct reg_cache *eice_cache; /**< Embedded ICE register cache */
uint32_t arm_bkpt; /**< ARM breakpoint instruction */
uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
......
......@@ -639,7 +639,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target)
static void arm7tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
......@@ -655,8 +655,8 @@ int arm7tdmi_examine(struct target_s *target)
if (!target_was_examined(target))
{
/* get pointers to arch-specific information */
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *t = embeddedice_build_reg_cache(target, arm7_9);
if (t == NULL)
return ERROR_FAIL;
......
......@@ -735,7 +735,7 @@ void arm9tdmi_disable_single_step(target_t *target)
static void arm9tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
......@@ -749,8 +749,8 @@ int arm9tdmi_examine(struct target_s *target)
if (!target_was_examined(target))
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *t;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *t;
/* one extra register (vector catch) */
t = embeddedice_build_reg_cache(target, arm7_9);
if (t == NULL)
......
......@@ -249,10 +249,10 @@ int armv4_5_invalidate_core_regs(target_t *target)
return ERROR_OK;
}
reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
struct reg_cache* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
{
int num_regs = 37;
reg_cache_t *cache = malloc(sizeof(reg_cache_t));
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
int i;
......
......@@ -87,7 +87,7 @@ enum
typedef struct arm
{
int common_magic;
reg_cache_t *core_cache;
struct reg_cache *core_cache;
int /* armv4_5_mode */ core_mode;
enum armv4_5_state core_state;
......@@ -135,7 +135,7 @@ struct armv4_5_core_reg
armv4_5_common_t *armv4_5_common;
};
reg_cache_t* armv4_5_build_reg_cache(target_t *target,
struct reg_cache* armv4_5_build_reg_cache(target_t *target,
armv4_5_common_t *armv4_5_common);
/* map psr mode bits to linear number */
......
......@@ -92,7 +92,7 @@ enum
struct armv7a_common
{
int common_magic;
reg_cache_t *core_cache;
struct reg_cache *core_cache;
enum armv7a_mode core_mode;
enum armv7a_state core_state;
......@@ -150,7 +150,7 @@ struct armv7a_core_reg
};
int armv7a_arch_state(struct target_s *target);
reg_cache_t *armv7a_build_reg_cache(target_t *target,
struct reg_cache *armv7a_build_reg_cache(target_t *target,
struct armv7a_common *armv7a_common);
int armv7a_register_commands(struct command_context_s *cmd_ctx);
int armv7a_init_arch_info(target_t *target, struct armv7a_common *armv7a);
......
......@@ -524,12 +524,12 @@ int armv7m_arch_state(struct target_s *target)
}
/** Builds cache of architecturally defined registers. */
reg_cache_t *armv7m_build_reg_cache(target_t *target)
struct reg_cache *armv7m_build_reg_cache(target_t *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int num_regs = ARMV7M_NUM_REGS;
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *cache = malloc(sizeof(reg_cache_t));
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
......
......@@ -94,7 +94,7 @@ enum
struct armv7m_common
{
int common_magic;
reg_cache_t *core_cache;
struct reg_cache *core_cache;
enum armv7m_mode core_mode;
int exception_number;
struct swjdp_common swjdp_info;
......@@ -134,7 +134,7 @@ struct armv7m_core_reg
struct armv7m_common *armv7m_common;
};
reg_cache_t *armv7m_build_reg_cache(target_t *target);
struct reg_cache *armv7m_build_reg_cache(target_t *target);
enum armv7m_mode armv7m_number_to_mode(int number);
int armv7m_mode_to_number(enum armv7m_mode mode);
......
......@@ -1435,7 +1435,7 @@ static int cortex_a8_examine(struct target_s *target)
static void cortex_a8_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
......
......@@ -1516,7 +1516,7 @@ static void
cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
{
uint32_t dwtcr;
struct reg_cache_s *cache;
struct reg_cache *cache;
cortex_m3_dwt_comparator_t *comparator;
int reg, i;
......
......@@ -158,7 +158,7 @@ struct cortex_m3_common
int dwt_num_comp;
int dwt_comp_available;
cortex_m3_dwt_comparator_t *dwt_comparator_list;
struct reg_cache_s *dwt_cache;
struct reg_cache *dwt_cache;
struct armv7m_common armv7m;
};
......
......@@ -163,11 +163,11 @@ static int embeddedice_get_reg(reg_t *reg)
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
reg_cache_t *
struct reg_cache *
embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
{
int retval;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = NULL;
struct embeddedice_reg *arch_info = NULL;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
......
......@@ -93,7 +93,7 @@ struct embeddedice_reg
struct arm_jtag *jtag_info;
};
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
struct reg_cache* embeddedice_build_reg_cache(target_t *target,
struct arm7_9_common *arm7_9);
int embeddedice_setup(target_t *target);
......
......@@ -121,9 +121,9 @@ static int etb_get_reg(reg_t *reg)
return ERROR_OK;
}
reg_cache_t* etb_build_reg_cache(etb_t *etb)
struct reg_cache* etb_build_reg_cache(etb_t *etb)
{
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = NULL;
struct etb_reg *arch_info = NULL;
int num_regs = 9;
......
......@@ -39,7 +39,7 @@ typedef struct etb_s
etm_context_t *etm_ctx;
struct jtag_tap *tap;
uint32_t cur_scan_chain;
reg_cache_t *reg_cache;
struct reg_cache *reg_cache;
/* ETB parameters */
uint32_t ram_depth;
......@@ -54,6 +54,6 @@ struct etb_reg
extern struct etm_capture_driver etb_capture_driver;
reg_cache_t* etb_build_reg_cache(etb_t *etb);
struct reg_cache* etb_build_reg_cache(etb_t *etb);
#endif /* ETB_H */
......@@ -231,7 +231,7 @@ static command_t *etm_cmd;
*/
static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
{
reg_cache_t *cache = etm_ctx->reg_cache;
struct reg_cache *cache = etm_ctx->reg_cache;
int i;
for (i = 0; i < cache->num_regs; i++) {
......@@ -248,7 +248,7 @@ static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
}
static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
reg_cache_t *cache, struct etm_reg *ereg,
struct reg_cache *cache, struct etm_reg *ereg,
const struct etm_reg_info *r, unsigned nreg)
{
reg_t *reg = cache->reg_list;
......@@ -279,10 +279,10 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
}
}
reg_cache_t *etm_build_reg_cache(target_t *target,
struct reg_cache *etm_build_reg_cache(target_t *target,
struct arm_jtag *jtag_info, etm_context_t *etm_ctx)
{
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = NULL;
struct etm_reg *arch_info = NULL;
unsigned bcd_vers, config;
......
......@@ -155,7 +155,7 @@ struct etmv1_trace_data
typedef struct etm
{
target_t *target; /* target this ETM is connected to */
reg_cache_t *reg_cache; /* ETM register cache */
struct reg_cache *reg_cache; /* ETM register cache */
struct etm_capture_driver *capture_driver; /* driver used to access ETM data */
void *capture_driver_priv; /* capture driver private data */
uint32_t trigger_percent; /* how much trace buffer to fill after trigger */
......@@ -207,7 +207,7 @@ typedef enum
BR_RSVD7 = 0x7, /* reserved */
} etmv1_branch_reason_t;
reg_cache_t* etm_build_reg_cache(target_t *target,
struct reg_cache* etm_build_reg_cache(target_t *target,
struct arm_jtag *jtag_info, etm_context_t *etm_ctx);
int etm_setup(target_t *target);
......
......@@ -271,14 +271,14 @@ int mips32_arch_state(struct target_s *target)
return ERROR_OK;
}
reg_cache_t *mips32_build_reg_cache(target_t *target)
struct reg_cache *mips32_build_reg_cache(target_t *target)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target->arch_info;
int num_regs = MIPS32NUMCOREREGS;
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *cache = malloc(sizeof(reg_cache_t));
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
int i;
......
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