Commit 687a9553 authored by oharboe's avatar oharboe
Browse files

From Michael Bruck

- bugfix in server.c
- removed unused parameter from jtag_add_ir_scan et al. This
wasn't necessary in hindsight but anyway.
- arm11 source committed but not not in Makefile.am/target.c for now.

git-svn-id: svn://svn.berlios.de/openocd/trunk@341 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 4edcbe0a
......@@ -148,7 +148,7 @@ int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, end_state, NULL);
jtag_add_ir_scan(1, &field, end_state);
free(field.out_value);
}
......@@ -174,7 +174,7 @@ u8 str9xpec_isc_status(int chain_pos)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
DEBUG("status: 0x%2.2x", status);
......@@ -266,7 +266,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
status = str9xpec_isc_status(chain_pos);
......@@ -409,7 +409,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_sleep(40000);
/* read blank check result */
......@@ -423,7 +423,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_PI, NULL);
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_execute_queue();
status = str9xpec_isc_status(chain_pos);
......@@ -525,7 +525,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
jtag_add_sleep(10);
......@@ -591,7 +591,7 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));
......@@ -677,7 +677,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
return ERROR_OK;
}
......@@ -766,7 +766,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
......@@ -784,7 +784,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
......@@ -826,7 +826,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
......@@ -844,7 +844,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
status = buf_get_u32(scanbuf, 0, 8);
......@@ -908,7 +908,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32);
......@@ -1033,7 +1033,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI, NULL);
jtag_add_dr_scan(1, &field, TAP_RTI);
/* small delay before polling */
jtag_add_sleep(50);
......@@ -1051,7 +1051,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, -1, NULL);
jtag_add_dr_scan(1, &field, -1);
jtag_execute_queue();
} while(!(status & ISC_STATUS_BUSY));
......
......@@ -379,7 +379,7 @@ void cmd_queue_free()
cmd_queue_pages = NULL;
}
int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
jtag_device_t *device;
......@@ -472,7 +472,7 @@ int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state,
return ERROR_OK;
}
int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
int i;
......@@ -526,7 +526,7 @@ int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state
return ERROR_OK;
}
int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
int i, j;
int bypass_devices = 0;
......@@ -625,7 +625,8 @@ int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state,
return ERROR_OK;
}
int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state, void *dummy_anachronism)
int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
int i;
jtag_command_t **last_cmd = jtag_get_last_command_p();
......@@ -1168,7 +1169,7 @@ int jtag_examine_chain()
buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
}
jtag_add_plain_dr_scan(1, &field, TAP_TLR, NULL);
jtag_add_plain_dr_scan(1, &field, TAP_TLR);
jtag_execute_queue();
for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++)
......@@ -1264,7 +1265,7 @@ int jtag_validate_chain()
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_plain_ir_scan(1, &field, TAP_TLR, NULL);
jtag_add_plain_ir_scan(1, &field, TAP_TLR);
jtag_execute_queue();
device = jtag_devices;
......@@ -1740,7 +1741,7 @@ int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
fields[i].in_handler_priv = NULL;
}
jtag_add_ir_scan(argc / 2, fields, -1, NULL);
jtag_add_ir_scan(argc / 2, fields, -1);
jtag_execute_queue();
for (i = 0; i < argc / 2; i++)
......@@ -1799,7 +1800,7 @@ int handle_drscan_command(struct command_context_s *cmd_ctx, char *cmd, char **a
}
}
jtag_add_dr_scan(num_fields, fields, -1, NULL);
jtag_add_dr_scan(num_fields, fields, -1);
jtag_execute_queue();
for (i = 0; i < argc / 2; i++)
......
......@@ -244,10 +244,10 @@ extern int jtag_init(struct command_context_s *cmd_ctx);
extern int jtag_register_commands(struct command_context_s *cmd_ctx);
/* JTAG interface, can be implemented with a software or hardware fifo */
extern int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate, void *dummy_anachronism);
extern int jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
/* execute a state transition within the JTAG standard, but the exact path
* path that is taken is undefined. Many implementations use precisely
* 7 clocks to perform a transition, but it could be more or less
......
......@@ -62,7 +62,7 @@ int virtex2_set_instr(int chain_pos, u32 new_instr)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, TAP_RTI, NULL);
jtag_add_ir_scan(1, &field, TAP_RTI);
free(field.out_value);
}
......@@ -94,7 +94,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD, NULL);
jtag_add_dr_scan(1, &scan_field, TAP_PD);
free(values);
......@@ -127,7 +127,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
while (num_words--)
{
scan_field.in_handler_priv = words++;
jtag_add_dr_scan(1, &scan_field, TAP_PD, NULL);
jtag_add_dr_scan(1, &scan_field, TAP_PD);
}
return ERROR_OK;
......@@ -189,7 +189,7 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
field.num_bits = bit_file.length * 8;
field.out_value = bit_file.data;
jtag_add_dr_scan(1, &field, TAP_PD, NULL);
jtag_add_dr_scan(1, &field, TAP_PD);
jtag_execute_queue();
jtag_add_statemove(TAP_TLR);
......
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "arm11.h"
#include "jtag.h"
#include "log.h"
#include <stdlib.h>
#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
#if 0
#define FNC_INFO DEBUG("-")
#else
#define FNC_INFO
#endif
#if 1
#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
#else
#define FNC_INFO_NOTIMPLEMENTED
#endif
static void arm11_on_enter_debug_state(arm11_common_t * arm11);
#define ARM11_HANDLER(x) \
.x = arm11_##x
target_type_t arm11_target =
{
.name = "arm11",
ARM11_HANDLER(poll),
ARM11_HANDLER(arch_state),
ARM11_HANDLER(target_request_data),
ARM11_HANDLER(halt),
ARM11_HANDLER(resume),
ARM11_HANDLER(step),
ARM11_HANDLER(assert_reset),
ARM11_HANDLER(deassert_reset),
ARM11_HANDLER(soft_reset_halt),
ARM11_HANDLER(prepare_reset_halt),
ARM11_HANDLER(get_gdb_reg_list),
ARM11_HANDLER(read_memory),
ARM11_HANDLER(write_memory),
ARM11_HANDLER(bulk_write_memory),
ARM11_HANDLER(checksum_memory),
ARM11_HANDLER(add_breakpoint),
ARM11_HANDLER(remove_breakpoint),
ARM11_HANDLER(add_watchpoint),
ARM11_HANDLER(remove_watchpoint),
ARM11_HANDLER(run_algorithm),
ARM11_HANDLER(register_commands),
ARM11_HANDLER(target_command),
ARM11_HANDLER(init_target),
ARM11_HANDLER(quit),
};
int arm11_regs_arch_type = -1;
enum arm11_regtype
{
ARM11_REGISTER_CORE,
ARM11_REGISTER_CPSR,
ARM11_REGISTER_FX,
ARM11_REGISTER_FPS,
ARM11_REGISTER_FIQ,
ARM11_REGISTER_SVC,
ARM11_REGISTER_ABT,
ARM11_REGISTER_IRQ,
ARM11_REGISTER_UND,
ARM11_REGISTER_MON,
ARM11_REGISTER_SPSR_FIQ,
ARM11_REGISTER_SPSR_SVC,
ARM11_REGISTER_SPSR_ABT,
ARM11_REGISTER_SPSR_IRQ,
ARM11_REGISTER_SPSR_UND,
ARM11_REGISTER_SPSR_MON,
/* debug regs */
ARM11_REGISTER_DSCR,
ARM11_REGISTER_WDTR,
ARM11_REGISTER_RDTR,
};
typedef struct arm11_reg_defs_s
{
char * name;
u32 num;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
/* update arm11_regcache_ids when changing this */
static const arm11_reg_defs_t arm11_reg_defs[] =
{
{"r0", 0, 0, ARM11_REGISTER_CORE},
{"r1", 1, 1, ARM11_REGISTER_CORE},
{"r2", 2, 2, ARM11_REGISTER_CORE},
{"r3", 3, 3, ARM11_REGISTER_CORE},
{"r4", 4, 4, ARM11_REGISTER_CORE},
{"r5", 5, 5, ARM11_REGISTER_CORE},
{"r6", 6, 6, ARM11_REGISTER_CORE},
{"r7", 7, 7, ARM11_REGISTER_CORE},
{"r8", 8, 8, ARM11_REGISTER_CORE},
{"r9", 9, 9, ARM11_REGISTER_CORE},
{"r10", 10, 10, ARM11_REGISTER_CORE},
{"r11", 11, 11, ARM11_REGISTER_CORE},
{"r12", 12, 12, ARM11_REGISTER_CORE},
{"sp", 13, 13, ARM11_REGISTER_CORE},
{"lr", 14, 14, ARM11_REGISTER_CORE},
{"pc", 15, 15, ARM11_REGISTER_CORE},
#if ARM11_REGCACHE_FREGS
{"f0", 0, 16, ARM11_REGISTER_FX},
{"f1", 1, 17, ARM11_REGISTER_FX},
{"f2", 2, 18, ARM11_REGISTER_FX},
{"f3", 3, 19, ARM11_REGISTER_FX},
{"f4", 4, 20, ARM11_REGISTER_FX},
{"f5", 5, 21, ARM11_REGISTER_FX},
{"f6", 6, 22, ARM11_REGISTER_FX},
{"f7", 7, 23, ARM11_REGISTER_FX},
{"fps", 0, 24, ARM11_REGISTER_FPS},
#endif
{"cpsr", 0, 25, ARM11_REGISTER_CPSR},
#if ARM11_REGCACHE_MODEREGS
{"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
{"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
{"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
{"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
{"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
{"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
{"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
{"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
{"r13_svc", 13, -1, ARM11_REGISTER_SVC},
{"r14_svc", 14, -1, ARM11_REGISTER_SVC},
{"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
{"r13_abt", 13, -1, ARM11_REGISTER_ABT},
{"r14_abt", 14, -1, ARM11_REGISTER_ABT},
{"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
{"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
{"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
{"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
{"r13_und", 13, -1, ARM11_REGISTER_UND},
{"r14_und", 14, -1, ARM11_REGISTER_UND},
{"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
/* ARM1176 only */
{"r13_mon", 13, -1, ARM11_REGISTER_MON},
{"r14_mon", 14, -1, ARM11_REGISTER_MON},
{"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
#endif
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
{"rdtr", 0, -1, ARM11_REGISTER_RDTR},
};
enum arm11_regcache_ids
{
ARM11_RC_R0,
ARM11_RC_RX = ARM11_RC_R0,
ARM11_RC_R1,
ARM11_RC_R2,
ARM11_RC_R3,
ARM11_RC_R4,
ARM11_RC_R5,
ARM11_RC_R6,
ARM11_RC_R7,
ARM11_RC_R8,
ARM11_RC_R9,
ARM11_RC_R10,
ARM11_RC_R11,
ARM11_RC_R12,
ARM11_RC_R13,
ARM11_RC_SP = ARM11_RC_R13,
ARM11_RC_R14,
ARM11_RC_LR = ARM11_RC_R14,
ARM11_RC_R15,
ARM11_RC_PC = ARM11_RC_R15,
#if ARM11_REGCACHE_FREGS
ARM11_RC_F0,
ARM11_RC_FX = ARM11_RC_F0,
ARM11_RC_F1,
ARM11_RC_F2,
ARM11_RC_F3,
ARM11_RC_F4,
ARM11_RC_F5,
ARM11_RC_F6,
ARM11_RC_F7,
ARM11_RC_FPS,
#endif
ARM11_RC_CPSR,
#if ARM11_REGCACHE_MODEREGS
ARM11_RC_R8_FIQ,
ARM11_RC_R9_FIQ,
ARM11_RC_R10_FIQ,
ARM11_RC_R11_FIQ,
ARM11_RC_R12_FIQ,
ARM11_RC_R13_FIQ,
ARM11_RC_R14_FIQ,
ARM11_RC_SPSR_FIQ,
ARM11_RC_R13_SVC,
ARM11_RC_R14_SVC,
ARM11_RC_SPSR_SVC,
ARM11_RC_R13_ABT,
ARM11_RC_R14_ABT,
ARM11_RC_SPSR_ABT,
ARM11_RC_R13_IRQ,
ARM11_RC_R14_IRQ,
ARM11_RC_SPSR_IRQ,
ARM11_RC_R13_UND,
ARM11_RC_R14_UND,
ARM11_RC_SPSR_UND,
ARM11_RC_R13_MON,
ARM11_RC_R14_MON,
ARM11_RC_SPSR_MON,
#endif
ARM11_RC_DSCR,
ARM11_RC_WDTR,
ARM11_RC_RDTR,
ARM11_RC_MAX,
};
#define ARM11_GDB_REGISTER_COUNT 26
u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t arm11_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
/** Check and if necessary take control of the system
*
* \param arm11 Target state variable.
* \param dscr If the current DSCR content is
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
u32 dscr_local_tmp_copy;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
*dscr = arm11_read_DSCR(arm11);
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
{
DEBUG("Bringing target into debug mode");
*dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
arm11_write_DSCR(arm11, *dscr);
/* add further reset initialization here */
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
arm11->target->state = TARGET_HALTED;
arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
}
else
{
arm11->target->state = TARGET_RUNNING;
arm11->target->debug_reason = DBG_REASON_NOTHALTED;
}
arm11_sc7_clear_bw(arm11);
}
}
#define R(x) \
(arm11->reg_values[ARM11_RC_##x])
/** Save processor state.
*
* This is called when the HALT instruction has succeeded
* or on other occasions that stop the processor.
*
*/
static void arm11_on_enter_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
{size_t i;
for(i = 0; i < asizeof(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
}}
/* Save DSCR */
R(DSCR) = arm11_read_DSCR(arm11);
/* Save wDTR */
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
{
arm11_add_debug_SCAN_N(arm11, 0x05, -1);