Commit 646ce814 authored by mkdorg@users.sourceforge.net's avatar mkdorg@users.sourceforge.net Committed by Øyvind Harboe
Browse files

target: add basic dsp563xx support

parent 46393669
...@@ -3157,6 +3157,8 @@ This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will ...@@ -3157,6 +3157,8 @@ This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
be detected and the normal reset behaviour used. be detected and the normal reset behaviour used.
@end itemize @end itemize
@item @code{dragonite} -- resembles arm966e @item @code{dragonite} -- resembles arm966e
@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
(Support for this is still incomplete.)
@item @code{fa526} -- resembles arm920 (w/o Thumb) @item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926 @item @code{feroceon} -- resembles arm926
@item @code{mips_m4k} -- a MIPS core. This supports one variant: @item @code{mips_m4k} -- a MIPS core. This supports one variant:
......
...@@ -33,7 +33,9 @@ libtarget_la_SOURCES = \ ...@@ -33,7 +33,9 @@ libtarget_la_SOURCES = \
$(ARMV7_SRC) \ $(ARMV7_SRC) \
$(ARM_MISC_SRC) \ $(ARM_MISC_SRC) \
$(MIPS32_SRC) \ $(MIPS32_SRC) \
avrt.c avrt.c \
dsp563xx.c \
dsp563xx_once.c
TARGET_CORE_SRC = \ TARGET_CORE_SRC = \
algorithm.c \ algorithm.c \
...@@ -120,6 +122,8 @@ noinst_HEADERS = \ ...@@ -120,6 +122,8 @@ noinst_HEADERS = \
armv7a.h \ armv7a.h \
armv7m.h \ armv7m.h \
avrt.h \ avrt.h \
dsp563xx.h \
dsp563xx_once.h \
breakpoints.h \ breakpoints.h \
cortex_m3.h \ cortex_m3.h \
cortex_a8.h \ cortex_a8.h \
......
This diff is collapsed.
/***************************************************************************
* Copyright (C) 2009 by Mathias Kuester *
* mkdorg@users.sourceforge.net *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef DSP563XX_H
#define DSP563XX_H
#include <jtag/jtag.h>
#define DSP563XX_NUMCOREREGS 44
struct mcu_jtag
{
struct jtag_tap *tap;
};
struct dsp563xx_pipeline_context
{
/* PIL Register */
uint32_t once_opilr;
/* PDB Register */
uint32_t once_opdbr;
};
struct dsp563xx_common
{
struct mcu_jtag jtag_info;
struct reg_cache *core_cache;
uint32_t core_regs[DSP563XX_NUMCOREREGS];
struct dsp563xx_pipeline_context pipeline_context;
/* register cache to processor synchronization */
int (*read_core_reg) (struct target * target, int num);
int (*write_core_reg) (struct target * target, int num);
};
struct dsp563xx_core_reg
{
uint32_t num;
char *name;
uint32_t size;
uint32_t r_cmd;
uint32_t w_cmd;
struct target *target;
struct dsp563xx_common *dsp563xx_common;
};
static inline struct dsp563xx_common *target_to_dsp563xx(struct target *target)
{
return target->arch_info;
}
int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out,
int ir_len, int rti);
int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out,
int dr_len, int rti);
int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
int ir_len, int rti);
int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
int dr_len, int rti);
int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out,
int ir_len, int rti);
int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out,
int dr_len, int rti);
int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
int ir_len, int rti);
int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
int dr_len, int rti);
int dsp563xx_execute_queue(void);
#endif /* DSP563XX_H */
/***************************************************************************
* Copyright (C) 2009 by Mathias Kuester *
* mkdorg@users.sourceforge.net *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/jim.h>
#include "target.h"
#include "target_type.h"
#include "register.h"
#include "dsp563xx.h"
#include "dsp563xx_once.h"
/** single word instruction */
int dsp563xx_once_ir_exec(struct jtag_tap *tap, uint8_t instr, uint8_t rw,
uint8_t go, uint8_t ex)
{
dsp563xx_write_dr_u8(tap, 0,
instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0);
dsp563xx_execute_queue();
return ERROR_OK;
}
/** single word instruction */
int dsp563xx_once_ir_exec_nq(struct jtag_tap *tap, uint8_t instr, uint8_t rw,
uint8_t go, uint8_t ex)
{
dsp563xx_write_dr_u8(tap, 0,
instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0);
return ERROR_OK;
}
/** once read register */
int dsp563xx_once_reg_read(struct jtag_tap *tap, uint8_t reg, uint32_t * data)
{
uint32_t dr_in;
dr_in = 0;
dsp563xx_once_ir_exec(tap, reg, 1, 0, 0);
dsp563xx_write_dr_u32(tap, &dr_in, 0x00, 24, 0);
dsp563xx_execute_queue();
*data = dr_in;
return ERROR_OK;
}
/** once write register */
int dsp563xx_once_reg_write(struct jtag_tap *tap, uint8_t reg, uint32_t data)
{
dsp563xx_once_ir_exec(tap, reg, 0, 0, 0);
dsp563xx_write_dr_u32(tap, 0x00, data, 24, 0);
dsp563xx_execute_queue();
return ERROR_OK;
}
/** single word instruction */
int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, uint32_t opcode)
{
dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0);
dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0);
dsp563xx_execute_queue();
return ERROR_OK;
}
/** double word instruction */
int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, uint32_t opcode,
uint32_t operand)
{
dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 0, 0);
dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0);
dsp563xx_execute_queue();
dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0);
dsp563xx_write_dr_u32(tap, 0, operand, 24, 0);
dsp563xx_execute_queue();
return ERROR_OK;
}
/** single word instruction */
int dsp563xx_once_execute_sw_ir_nq(struct jtag_tap *tap, uint32_t opcode)
{
dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0);
dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0);
return ERROR_OK;
}
/** double word instruction */
int dsp563xx_once_execute_dw_ir_nq(struct jtag_tap *tap, uint32_t opcode,
uint32_t operand)
{
dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 0, 0);
dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0);
dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0);
dsp563xx_write_dr_u32(tap, 0, operand, 24, 0);
return ERROR_OK;
}
/***************************************************************************
* Copyright (C) 2009 by Mathias Kuester *
* mkdorg@users.sourceforge.net *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef DSP563XX_ONCE_H
#define DSP563XX_ONCE_H
#include <jtag/jtag.h>
#define DSP563XX_ONCE_OCR_EX (1<<5)
#define DSP563XX_ONCE_OCR_GO (1<<6)
#define DSP563XX_ONCE_OCR_RW (1<<7)
#define DSP563XX_ONCE_OSCR_OS1 (1<<7)
#define DSP563XX_ONCE_OSCR_OS0 (1<<6)
#define DSP563XX_ONCE_OSCR_HIT (1<<5)
#define DSP563XX_ONCE_OSCR_TO (1<<4)
#define DSP563XX_ONCE_OSCR_MBO (1<<3)
#define DSP563XX_ONCE_OSCR_SWO (1<<2)
#define DSP563XX_ONCE_OSCR_IME (1<<1)
#define DSP563XX_ONCE_OSCR_TME (1<<0)
#define DSP563XX_ONCE_OSCR_NORMAL_M (0)
#define DSP563XX_ONCE_OSCR_STOPWAIT_M (DSP563XX_ONCE_OSCR_OS0)
#define DSP563XX_ONCE_OSCR_BUSY_M (DSP563XX_ONCE_OSCR_OS1)
#define DSP563XX_ONCE_OSCR_DEBUG_M (DSP563XX_ONCE_OSCR_OS0|DSP563XX_ONCE_OSCR_OS1)
#define DSP563XX_ONCE_OSCR 0x000 /* status/ctrl reg. */
#define DSP563XX_ONCE_OMBC 0x001 /* memory breakp. reg. */
#define DSP563XX_ONCE_OBCR 0x002 /* breakp. ctrl reg */
#define DSP563XX_ONCE_OMLR0 0x005 /* memory limit reg */
#define DSP563XX_ONCE_OMLR1 0x006 /* memory limit reg */
#define DSP563XX_ONCE_OGDBR 0x009 /* gdb reg */
#define DSP563XX_ONCE_OPDBR 0x00A /* pdb reg */
#define DSP563XX_ONCE_OPILR 0x00B /* pil reg */
#define DSP563XX_ONCE_PDBGOTO 0x00C /* pdb to go reg */
#define DSP563XX_ONCE_OTC 0x00D /* trace cnt */
#define DSP563XX_ONCE_TAGB 0x00E /* tags buffer */
#define DSP563XX_ONCE_OPABFR 0x00F /* pab fetch reg */
#define DSP563XX_ONCE_OPABDR 0x010 /* pab decode reg */
#define DSP563XX_ONCE_OPABEX 0x011 /* pab exec reg */
#define DSP563XX_ONCE_OPABEX 0x011 /* trace buffer/inc ptr */
#define DSP563XX_ONCE_NOREG 0x01F /* no register selected */
/** single word instruction */
int dsp563xx_once_ir_exec(struct jtag_tap *tap, uint8_t instr, uint8_t rw,
uint8_t go, uint8_t ex);
/** single word instruction */
int dsp563xx_once_ir_exec_nq(struct jtag_tap *tap, uint8_t instr, uint8_t rw,
uint8_t go, uint8_t ex);
/** once read register */
int dsp563xx_once_reg_read(struct jtag_tap *tap, uint8_t reg, uint32_t * data);
/** once write register */
int dsp563xx_once_reg_write(struct jtag_tap *tap, uint8_t reg, uint32_t data);
/** single word instruction */
int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, uint32_t opcode);
/** double word instruction */
int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, uint32_t opcode,
uint32_t operand);
/** single word instruction */
int dsp563xx_once_execute_sw_ir_nq(struct jtag_tap *tap, uint32_t opcode);
/** double word instruction */
int dsp563xx_once_execute_dw_ir_nq(struct jtag_tap *tap, uint32_t opcode,
uint32_t operand);
#endif /* DSP563XX_ONCE_H */
...@@ -64,6 +64,7 @@ extern struct target_type cortexa8_target; ...@@ -64,6 +64,7 @@ extern struct target_type cortexa8_target;
extern struct target_type arm11_target; extern struct target_type arm11_target;
extern struct target_type mips_m4k_target; extern struct target_type mips_m4k_target;
extern struct target_type avr_target; extern struct target_type avr_target;
extern struct target_type dsp563xx_target;
extern struct target_type testee_target; extern struct target_type testee_target;
struct target_type *target_types[] = struct target_type *target_types[] =
...@@ -83,6 +84,7 @@ struct target_type *target_types[] = ...@@ -83,6 +84,7 @@ struct target_type *target_types[] =
&arm11_target, &arm11_target,
&mips_m4k_target, &mips_m4k_target,
&avr_target, &avr_target,
&dsp563xx_target,
&testee_target, &testee_target,
NULL, NULL,
}; };
......
#
# Olimex ARM-USB-OCD-TINY
#
# http://www.olimex.com/dev/arm-usb-tiny.html
#
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG TINY"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15ba 0x0004
# Script for freescale DSP56321
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dsp56321
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a big endian
set _ENDIAN big
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0x1181501d
}
#jtag speed
jtag_khz 4500
#has only srst
reset_config srst_only
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID
#target configuration
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME
#working area at base of ram
$_TARGETNAME configure -work-area-virt 0
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