Commit 53d605e1 authored by zwelch's avatar zwelch
Browse files

- Fixes '!=' whitespace

- Replace ')\(!=\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\(!=\)(' with '\1 \2 ('.
- Replace '\(\w\)\(!=\)\(\w\)' with '\1 \2 \3'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2363 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 5e98c714
......@@ -64,7 +64,7 @@ static int autodetect_image_type(image_t *image, char *url)
}
fileio_close(&fileio);
if (retval!=ERROR_OK)
if (retval != ERROR_OK)
return retval;
/* check header against known signatures */
......@@ -362,7 +362,7 @@ static int image_elf_read_headers(image_t *image)
return ERROR_FILEIO_OPERATION_FAILED;
}
if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG)!=0)
if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG) != 0)
{
LOG_ERROR("invalid ELF file, bad magic number");
return ERROR_IMAGE_FORMAT_ERROR;
......@@ -374,8 +374,8 @@ static int image_elf_read_headers(image_t *image)
}
elf->endianness = elf->header->e_ident[EI_DATA];
if ((elf->endianness!=ELFDATA2LSB)
&&(elf->endianness!=ELFDATA2MSB))
if ((elf->endianness != ELFDATA2LSB)
&&(elf->endianness != ELFDATA2MSB))
{
LOG_ERROR("invalid ELF file, unknown endianess setting");
return ERROR_IMAGE_FORMAT_ERROR;
......
......@@ -314,7 +314,7 @@ int mips_m4k_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
......
......@@ -1088,7 +1088,7 @@ int target_arch_state(struct target_s *target)
LOG_USER("target state: %s",
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
if (target->state!=TARGET_HALTED)
if (target->state != TARGET_HALTED)
return ERROR_OK;
retval=target->type->arch_state(target);
......@@ -1584,7 +1584,7 @@ static int sense_handler(void)
static int prevPowerdropout = 0;
int retval;
if ((retval=jtag_power_dropout(&powerDropout))!=ERROR_OK)
if ((retval=jtag_power_dropout(&powerDropout)) != ERROR_OK)
return retval;
int powerRestored;
......@@ -1603,7 +1603,7 @@ static int sense_handler(void)
lastPower = current;
}
if ((retval=jtag_srst_asserted(&srstAsserted))!=ERROR_OK)
if ((retval=jtag_srst_asserted(&srstAsserted)) != ERROR_OK)
return retval;
int srstDeasserted;
......@@ -1909,7 +1909,7 @@ int target_wait_state(target_t *target, enum target_state state, int ms)
for (;;)
{
if ((retval=target_poll(target))!=ERROR_OK)
if ((retval=target_poll(target)) != ERROR_OK)
return retval;
if (target->state == state)
{
......@@ -2872,7 +2872,7 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, char *filename)
/*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */
char *data=malloc(2*length);
if (data!=NULL)
if (data != NULL)
{
for (i=0; i<length;i++)
{
......@@ -2903,7 +2903,7 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd,
struct timeval timeout, now;
gettimeofday(&timeout, NULL);
if (argc!=2)
if (argc != 2)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
......@@ -2949,7 +2949,7 @@ static int handle_profile_command(struct command_context_s *cmd_ctx, char *cmd,
retval=ERROR_OK;
break;
}
if (retval!=ERROR_OK)
if (retval != ERROR_OK)
{
break;
}
......@@ -3388,7 +3388,7 @@ void target_handle_event( target_t *target, enum target_event e )
e,
Jim_Nvp_value2name_simple( nvp_target_event, e )->name,
Jim_GetString( teap->body, NULL ) );
if (Jim_EvalObj( interp, teap->body )!=JIM_OK)
if (Jim_EvalObj( interp, teap->body ) != JIM_OK)
{
Jim_PrintErrorMessage(interp);
}
......@@ -4386,7 +4386,7 @@ static struct FastLoad *fastload;
static void free_fastload(void)
{
if (fastload!=NULL)
if (fastload != NULL)
{
int i;
for (i=0; i<fastload_num; i++)
......@@ -4504,7 +4504,7 @@ static int handle_fast_load_image_command(struct command_context_s *cmd_ctx, cha
image_close(&image);
if (retval!=ERROR_OK)
if (retval != ERROR_OK)
{
free_fastload();
}
......
......@@ -889,7 +889,7 @@ int xscale_update_vectors(target_t *target)
retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval!=ERROR_OK)
if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
......@@ -908,7 +908,7 @@ int xscale_update_vectors(target_t *target)
retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
if (retval!=ERROR_OK)
if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
......@@ -1028,11 +1028,11 @@ int xscale_debug_entry(target_t *target)
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
/* get r0, pc, r1 to r7 and cpsr */
if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
if ((retval=xscale_receive(target, buffer, 10)) != ERROR_OK)
return retval;
/* move r0 from buffer to register cache */
......@@ -1253,7 +1253,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
}
}
if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK)
if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
return retval;
return ERROR_OK;
......@@ -1266,7 +1266,7 @@ int xscale_disable_single_step(struct target_s *target)
reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK)
if ((retval=xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
return retval;
return ERROR_OK;
......@@ -1297,7 +1297,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha
}
/* update vector tables */
if ((retval=xscale_update_vectors(target))!=ERROR_OK)
if ((retval=xscale_update_vectors(target)) != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
......@@ -1451,56 +1451,56 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr
}
LOG_DEBUG("enable single-step");
if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK)
if ((retval=xscale_enable_single_step(target, next_pc)) != ERROR_OK)
return retval;
/* restore banked registers */
if ((retval=xscale_restore_context(target))!=ERROR_OK)
if ((retval=xscale_restore_context(target)) != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.buffer_enabled)
{
if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x62)) != ERROR_OK)
return retval;
if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x31)) != ERROR_OK)
return retval;
}
else
if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x30)) != ERROR_OK)
return retval;
/* send CPSR */
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK)
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK)
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK)
if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK)
if ((retval=armv4_5_invalidate_core_regs(target)) != ERROR_OK)
return retval;
/* wait for and process debug entry */
if ((retval=xscale_debug_entry(target))!=ERROR_OK)
if ((retval=xscale_debug_entry(target)) != ERROR_OK)
return retval;
LOG_DEBUG("disable single-step");
if ((retval=xscale_disable_single_step(target))!=ERROR_OK)
if ((retval=xscale_disable_single_step(target)) != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
......@@ -1531,7 +1531,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK)
if ((retval=arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
......@@ -1545,7 +1545,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK)
if ((retval=xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
return retval;
}
......@@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
......@@ -1930,20 +1930,20 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words */
if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
if ((retval=xscale_receive(target, buf32, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
......@@ -1971,12 +1971,12 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
......@@ -2007,15 +2007,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words to be written*/
if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
......@@ -2045,16 +2045,16 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
}
}
#endif
if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
if ((retval=xscale_send(target, buffer, count, size)) != ERROR_OK)
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
......
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