Commit 4a5f45e8 authored by drath's avatar drath
Browse files

- merged XScale branch back into trunk

- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c
- free working area and register stuff if str7x block write algorithm failed
- check PC after exiting a target algorithm in armv4_5.c


git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 5ed126c4
......@@ -451,7 +451,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
u32 address = bank->base + offset;
reg_param_t reg_params[5];
armv4_5_algorithm_t armv4_5_info;
int retval;
int retval = ERROR_OK;
u32 str7x_flash_write_code[] = {
/* write: */
......@@ -537,12 +537,13 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
if ((retval = target->type->run_algorithm(target, 0, NULL, 5, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
ERROR("error executing str7x flash write algorithm");
return ERROR_FLASH_OPERATION_FAILED;
break;
}
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
{
return ERROR_FLASH_OPERATION_FAILED;
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
buffer += thisrun_count * 8;
......@@ -558,7 +559,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
return ERROR_OK;
return retval;
}
int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
......
......@@ -242,22 +242,23 @@ int fileio_open(fileio_t *fileio, char *url, enum fileio_access access,
enum fileio_pri_type pri_type, void *pri_info, enum fileio_sec_type sec_type)
{
int retval = ERROR_OK;
char *resource_identifier = NULL;
if ((!url) || (strlen(url) < 3))
/* try to identify file location */
if ((resource_identifier = strstr(url, "bootp://")) && (resource_identifier == url))
{
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "invalid file url");
return ERROR_INVALID_ARGUMENTS;
ERROR("bootp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
if ((url[0] == '/') || (isalpha(url[0])) || ((url[1] == ':') && (url[2] == '\\')))
else if ((resource_identifier = strstr(url, "tftp://")) && (resource_identifier == url))
{
fileio->location = FILEIO_LOCAL;
ERROR("tftp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
else
{
ERROR("couldn't identify resource location from URL '%s'", url);
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "couldn't identify resource location from URL '%s'", url);
return ERROR_FILEIO_LOCATION_UNKNOWN;
/* default to local files */
fileio->location = FILEIO_LOCAL;
}
fileio->access = access;
......
......@@ -385,7 +385,7 @@ int amt_jtagaccel_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;
......
......@@ -248,7 +248,7 @@ int bitbang_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;
......
......@@ -375,7 +375,7 @@ int parport_init(void)
dataport = parport_port;
statusport = parport_port + 1;
DEBUG("requesting privileges for parallel port 0x%x...", dataport);
DEBUG("requesting privileges for parallel port 0x%lx...", dataport);
#if PARPORT_USE_GIVEIO == 1
if (parport_get_giveio_access() != 0)
#else /* PARPORT_USE_GIVEIO */
......
......@@ -18,7 +18,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-15 14:30 CET)"
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-28 18:30 CEST)"
#ifdef HAVE_CONFIG_H
#include "config.h"
......
......@@ -3,7 +3,7 @@ METASOURCES = AUTO
noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c etb.c
arm966e.c arm926ejs.c etb.c xscale.c arm_simulator.c
noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h
......@@ -835,6 +835,9 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
address, opcode, COND(opcode), Rm);
instruction->info.b_bl_bx_blx.reg_operand = Rm;
instruction->info.b_bl_bx_blx.target_address = -1;
}
/* Enhanced DSP add/subtracts */
......@@ -1078,6 +1081,18 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
/* LSR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x1) && (shift_imm == 0x0))
shift_imm = 0x20;
/* ASR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x2) && (shift_imm == 0x0))
shift_imm = 0x20;
/* ROR by 32 bit is actually a RRX */
if ((shift == 0x3) && (shift_imm == 0x0))
shift = 0x4;
if ((shift_imm == 0x0) && (shift == 0x0))
{
snprintf(shifter_operand, 32, "r%i", Rm);
......@@ -1090,23 +1105,20 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
}
else if (shift == 0x1) /* LSR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm);
}
else if (shift == 0x2) /* ASR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
if (shift_imm == 0x0) /* RRX */
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
else
snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
}
else if (shift == 0x4) /* RRX */
{
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
}
}
}
else /* Register shifts ("<Rm>, <shift> <Rs>") */
......@@ -1130,7 +1142,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
{
snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
}
......@@ -1159,7 +1171,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
return ERROR_OK;
}
int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
{
/* clear fields, to avoid confusion */
memset(instruction, 0, sizeof(arm_instruction_t));
......@@ -1302,3 +1314,4 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
ERROR("should never reach this point");
return -1;
}
......@@ -126,16 +126,10 @@ typedef struct arm_b_bl_bx_blx_instr_s
u32 target_address;
} arm_b_bl_bx_blx_instr_t;
typedef struct arm_data_proc_instr_s
union arm_shifter_operand
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
u8 S;
u8 Rn;
u8 Rd;
union
{
struct {
u8 immediate;
u32 immediate;
} immediate;
struct {
u8 Rm;
......@@ -147,7 +141,15 @@ typedef struct arm_data_proc_instr_s
u8 shift;
u8 Rs;
} register_shift;
} shifter_operand;
};
typedef struct arm_data_proc_instr_s
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
u8 S;
u8 Rn;
u8 Rd;
union arm_shifter_operand shifter_operand;
} arm_data_proc_instr_t;
typedef struct arm_load_store_instr_s
......@@ -192,7 +194,7 @@ typedef struct arm_instruction_s
} arm_instruction_t;
extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
......
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "target.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
#include "log.h"
#include "binarybuffer.h"
#include <string.h>
u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
{
u32 return_value;
shift_amount &= 0xff;
if (shift == 0x0) /* LSL */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
return_value = Rm << shift_amount;
*carry = Rm >> (32 - shift_amount);
}
else if (shift_amount > 32)
{
return_value = 0x0;
*carry = 0x0;
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x1) /* LSR */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
return_value = Rm >> shift_amount;
*carry = (Rm >> (shift_amount - 1)) & 1;
}
else if (shift_amount > 32)
{
return_value = 0x0;
*carry = 0x0;
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x2) /* ASR */
{
if ((shift_amount > 0) && (shift_amount <= 32))
{
/* right shifts of unsigned values are guaranteed to be logical (shift in zeroes)
* simulate an arithmetic shift (shift in signed-bit) by adding the signed-bit manually */
return_value = Rm >> shift_amount;
if (Rm & 0x80000000)
return_value |= 0xffffffff << (32 - shift_amount);
}
else if (shift_amount > 32)
{
if (Rm & 0x80000000)
{
return_value = 0xffffffff;
*carry = 0x1;
}
else
{
return_value = 0x0;
*carry = 0x0;
}
}
else /* (shift_amount == 0) */
{
return_value = Rm;
}
}
else if (shift == 0x3) /* ROR */
{
if (shift_amount == 0)
{
return_value = Rm;
}
else
{
shift_amount = shift_amount % 32;
return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
*carry = (return_value >> 31) & 0x1;
}
}
else if (shift == 0x4) /* RRX */
{
return_value = Rm >> 1;
if (*carry)
Rm |= 0x80000000;
*carry = Rm & 0x1;
}
return return_value;
}
u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, u8 *shifter_carry_out)
{
u32 return_value;
int instruction_size;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
instruction_size = 4;
else
instruction_size = 2;
*shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
if (variant == 0) /* 32-bit immediate */
{
return_value = shifter_operand.immediate.immediate;
}
else if (variant == 1) /* immediate shift */
{
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.immediate_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
}
else if (variant == 2) /* register shift */
{
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
u32 Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
/* adjust RM in case the PC is being read */
if (shifter_operand.register_shift.Rm == 15)
Rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
}
else
{
ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
return return_value;
}
int pass_condition(u32 cpsr, u32 opcode)
{
switch ((opcode & 0xf0000000) >> 28)
{
case 0x0: /* EQ */
if (cpsr & 0x40000000)
return 1;
else
return 0;
case 0x1: /* NE */
if (!(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x2: /* CS */
if (cpsr & 0x20000000)
return 1;
else
return 0;
case 0x3: /* CC */
if (!(cpsr & 0x20000000))
return 1;
else
return 0;
case 0x4: /* MI */
if (cpsr & 0x80000000)
return 1;
else
return 0;
case 0x5: /* PL */
if (!(cpsr & 0x80000000))
return 1;
else
return 0;
case 0x6: /* VS */
if (cpsr & 0x10000000)
return 1;
else
return 0;
case 0x7: /* VC */
if (!(cpsr & 0x10000000))
return 1;
else
return 0;
case 0x8: /* HI */
if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x9: /* LS */
if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
return 1;
else
return 0;
case 0xa: /* GE */
if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xb: /* LT */
if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xc: /* GT */
if (!(cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xd: /* LE */
if ((cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xe:
case 0xf:
return 1;
}
ERROR("BUG: should never get here");
return 0;
}
/* simulate a single step (if possible)
* if the dry_run_pc argument is provided, no state is changed,
* but the new pc is stored in the variable pointed at by the argument
*/
int arm_simulate_step(target_t *target, u32 *dry_run_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
u32 opcode;
u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
arm_instruction_t instruction;
int instruction_size;
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
/* get current instruction, and identify it */
target_read_u32(target, current_pc, &opcode);
arm_evaluate_opcode(opcode, current_pc, &instruction);
instruction_size = 4;
}
else
{
/* TODO: add support for Thumb instruction set */
instruction_size = 2;
}
/* check condition code */
if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
{
if (dry_run_pc)
{
*dry_run_pc = current_pc + instruction_size;
}
else
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
}
return ERROR_OK;
}
/* examine instruction type */
/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
u32 target;
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
target = instruction.info.b_bl_bx_blx.target_address;
}
else
{
target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
}
if (dry_run_pc)
{
*dry_run_pc = target;
return ERROR_OK;
}
else
{
if (instruction.type == ARM_B)
{
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
}
else if (instruction.type == ARM_BL)
{
u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
}
else if (instruction.type == ARM_BX)
{
if (target & 0x1)
{
armv4_5->core_state = ARMV4_5_STATE_THUMB;
}
else
{
armv4_5->core_state = ARMV4_5_STATE_ARM;
}
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
}
else if (instruction.type == ARM_BLX)
{
u32 old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
if (target & 0x1)
{
armv4_5->core_state = ARMV4_5_STATE_THUMB;
}
else
{
armv4_5->core_state = ARMV4_5_STATE_ARM;
}
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
}
return ERROR_OK;
}
}
/* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
{
u32 Rd, Rn, shifter_operand;
u8 C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
u8 carry_out;