Commit 489eaadf authored by Marc Schink's avatar Marc Schink Committed by Tomas Vanek
Browse files

target/dsp563xx: Use 'bool' data type



Change-Id: Ie7ee82bf04c76ef899ae8b19105158e71b69ae2c
Signed-off-by: default avatarMarc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4962


Tested-by: jenkins
Reviewed-by: default avatarAntonio Borneo <borneo.antonio@gmail.com>
parent 8d748f42
......@@ -384,8 +384,8 @@ static int dsp563xx_read_core_reg(struct target *target, int num)
reg_value = dsp563xx->core_regs[num];
buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
dsp563xx->core_cache->reg_list[num].valid = 1;
dsp563xx->core_cache->reg_list[num].dirty = 0;
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
......@@ -400,8 +400,8 @@ static int dsp563xx_write_core_reg(struct target *target, int num)
reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
dsp563xx->core_regs[num] = reg_value;
dsp563xx->core_cache->reg_list[num].valid = 1;
dsp563xx->core_cache->reg_list[num].dirty = 0;
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
......@@ -432,8 +432,8 @@ static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, reg->size, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
......@@ -473,8 +473,8 @@ static void dsp563xx_build_reg_cache(struct target *target)
reg_list[i].name = dsp563xx_regs[i].name;
reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].type = &dsp563xx_reg_type;
reg_list[i].arch_info = &arch_info[i];
}
......@@ -508,7 +508,7 @@ static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask,
if (err != ERROR_OK)
return err;
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
......@@ -534,7 +534,7 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask
return err;
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
......@@ -745,7 +745,7 @@ static int dsp563xx_read_register(struct target *target, int num, int force)
struct dsp563xx_core_reg *arch_info;
if (force)
dsp563xx->core_cache->reg_list[num].valid = 0;
dsp563xx->core_cache->reg_list[num].valid = false;
if (!dsp563xx->core_cache->reg_list[num].valid) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
......@@ -795,7 +795,7 @@ static int dsp563xx_write_register(struct target *target, int num, int force)
struct dsp563xx_core_reg *arch_info;
if (force)
dsp563xx->core_cache->reg_list[num].dirty = 1;
dsp563xx->core_cache->reg_list[num].dirty = true;
if (dsp563xx->core_cache->reg_list[num].dirty) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
......@@ -884,8 +884,8 @@ static void dsp563xx_invalidate_x_context(struct target *target,
if ((arch_info->instr_mask >= addr_start) &&
(arch_info->instr_mask <= addr_end)) {
dsp563xx->core_cache->reg_list[i].valid = 0;
dsp563xx->core_cache->reg_list[i].dirty = 0;
dsp563xx->core_cache->reg_list[i].valid = false;
dsp563xx->core_cache->reg_list[i].dirty = false;
}
}
}
......@@ -985,7 +985,7 @@ static int dsp563xx_debug_init(struct target *target)
err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr);
if (err != ERROR_OK)
return err;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
}
err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0);
......@@ -1007,7 +1007,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
......@@ -1015,7 +1015,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
......@@ -1023,7 +1023,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
......@@ -1031,7 +1031,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
err = dsp563xx_save_context(target);
if (err != ERROR_OK)
......@@ -1552,9 +1552,9 @@ static int dsp563xx_read_memory_core(struct target *target,
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
......@@ -1734,9 +1734,9 @@ static int dsp563xx_write_memory_core(struct target *target,
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
......
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