Commit 4592506b authored by Aaron Carroll's avatar Aaron Carroll Committed by Øyvind Harboe
Browse files

TCL configs for OMAP4430 and Pandaboard


Signed-off-by: default avatarAaron Carroll <aaronc@cse.unsw.edu.au>
parent c34e69cb
jtag_rclk 6000
source [find target/omap4430.cfg]
reset_config trst_only
# OMAP4430
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap4430
}
# Although the OMAP4430 supposedly has an ICEpick-D, only the
# ICEpick-C router commands seem to work.
# See http://processors.wiki.ti.com/index.php/ICEPICK
source [find target/icepick.cfg]
#
# A9 DAP
#
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x3BA00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 9"
#
# M3 DAPs, one per core
#
if { [info exists M3_DAP_TAPID ] } {
set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
set _M3_DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m31_dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 5"
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m30_dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 4"
#
# ICEpick-D JRC (JTAG route controller)
#
if { [info exists JRC_TAPID ] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x3b95c02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
# Required by ICEpick to power-up the debug domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
#
# GDB target: Cortex-A9, using DAP
#
# The debugger can connect to either core of the A9, but currently
# not both simultaneously. Change -coreid to 1 to connect to the
# second core.
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a9 -chain-position $_CHIPNAME.dap -coreid 0
# SRAM: 56KiB at 0x4030.0000
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
#
# M3 targets, separate TAP/DAP for each core
#
target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
# Once the JRC is up, enable our TAPs
jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.dap
jtag tapenable $_CHIPNAME.m30_dap
jtag tapenable $_CHIPNAME.m31_dap
"
proc omap4_dbginit {target} {
# General Cortex A9 debug initialisation
cortex_a9 dbginit
}
$_TARGETNAME configure -event reset-assert-post "omap4_dbginit $_TARGETNAME"
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
set PRM_RSTCTRL 0x4A307B00
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 0x1"
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