Commit 3a550e5b authored by Spencer Oliver's avatar Spencer Oliver
Browse files

cleanup: rename armv4_5 to arm for readability



Nothing more than a name change, just to make reading
the code a bit simpler.

Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45
Signed-off-by: default avatarSpencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/390


Tested-by: jenkins
Reviewed-by: default avatarØyvind Harboe <oyvindharboe@gmail.com>
parent 9db46581
......@@ -97,7 +97,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
{
struct target *target = nand->target;
struct arm_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct arm *arm = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit_var = 0;
......@@ -152,7 +152,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
if (armv4_5->is_armv4)
if (arm->is_armv4)
exit_var = nand->copy_area->address + sizeof(code) - 4;
/* use alg to write data from work area to NAND chip */
......@@ -181,7 +181,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
{
struct target *target = nand->target;
struct arm_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct arm *arm = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit_var = 0;
......@@ -228,7 +228,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
if (armv4_5->is_armv4)
if (arm->is_armv4)
exit_var = nand->copy_area->address + sizeof(code) - 4;
/* use alg to write data from NAND chip to work area */
......
......@@ -286,7 +286,7 @@ static int str9xpec_build_block_list(struct flash_bank *bank)
FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
{
struct str9xpec_flash_controller *str9xpec_info;
struct arm *armv4_5 = NULL;
struct arm *arm = NULL;
struct arm7_9_common *arm7_9 = NULL;
struct arm_jtag *jtag_info = NULL;
......@@ -301,8 +301,8 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
/* REVISIT verify that the jtag position of flash controller is
* right after *THIS* core, which must be a STR9xx core ...
*/
armv4_5 = bank->target->arch_info;
arm7_9 = armv4_5->arch_info;
arm = bank->target->arch_info;
arm7_9 = arm->arch_info;
jtag_info = &arm7_9->jtag_info;
/* The core is the next tap after the flash controller in the chain */
......
......@@ -197,7 +197,7 @@ struct arm_reg {
int num;
enum arm_mode mode;
struct target *target;
struct arm *armv4_5_common;
struct arm *arm;
uint32_t value;
};
......
......@@ -340,8 +340,7 @@ static int arm720t_soft_reset_halt(struct target *target)
struct arm720t_common *arm720t = target_to_arm720(target);
struct reg *dbg_stat = &arm720t->arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
struct arm *armv4_5 = &arm720t->arm7_9_common
.armv4_5_common;
struct arm *arm = &arm720t->arm7_9_common.arm;
if ((retval = target_halt(target)) != ERROR_OK)
{
......@@ -382,16 +381,16 @@ static int arm720t_soft_reset_halt(struct target *target)
/* SVC, ARM state, IRQ and FIQ disabled */
uint32_t cpsr;
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(armv4_5, cpsr);
armv4_5->cpsr->dirty = 1;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
......@@ -428,8 +427,8 @@ static int arm720t_init_arch_info(struct target *target,
{
struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
arm7_9->armv4_5_common.mrc = arm720t_mrc;
arm7_9->armv4_5_common.mcr = arm720t_mcr;
arm7_9->arm.mrc = arm720t_mrc;
arm7_9->arm.mcr = arm720t_mcr;
arm7tdmi_init_arch_info(target, arm7_9, tap);
......@@ -454,7 +453,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp)
{
struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
arm720t->arm7_9_common.arm.is_armv4 = true;
return arm720t_init_arch_info(target, arm720t, target->tap);
}
......
......@@ -39,7 +39,7 @@ static inline struct arm720t_common *
target_to_arm720(struct target *target)
{
return container_of(target->arch_info, struct arm720t_common,
arm7_9_common.armv4_5_common);
arm7_9_common.arm);
}
#endif /* ARM720T_H */
This diff is collapsed.
......@@ -39,7 +39,7 @@
*/
struct arm7_9_common
{
struct arm armv4_5_common;
struct arm arm;
uint32_t common_magic;
struct arm_jtag jtag_info; /**< JTAG information for target */
......@@ -109,7 +109,7 @@ static inline struct arm7_9_common *
target_to_arm7_9(struct target *target)
{
return container_of(target->arch_info, struct arm7_9_common,
armv4_5_common);
arm);
}
static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
......
......@@ -586,7 +586,7 @@ static void arm7tdmi_branch_resume(struct target *target)
static void arm7tdmi_branch_resume_thumb(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
......@@ -603,7 +603,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
arm7tdmi_clock_out(jtag_info,
buf_get_u32(armv4_5->pc->value, 0, 32) | 1, NULL, 0);
buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0);
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
......@@ -631,7 +631,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
/* fetch NOP, LDR in Execute */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
......@@ -647,9 +647,9 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
static void arm7tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
struct arm *arm = target_to_arm(target);
(*cache_p) = arm_build_reg_cache(target, armv4_5);
(*cache_p) = arm_build_reg_cache(target, arm);
}
int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
......@@ -713,7 +713,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
arm7_9 = calloc(1,sizeof(struct arm7_9_common));
arm7tdmi_init_arch_info(target, arm7_9, target->tap);
arm7_9->armv4_5_common.is_armv4 = true;
arm7_9->arm.is_armv4 = true;
return ERROR_OK;
}
......
......@@ -246,11 +246,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
struct arm *armv4_5 = target_to_arm(target);
struct arm *arm = target_to_arm(target);
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
struct reg *r = armv4_5->core_cache->reg_list;
struct reg *r = arm->core_cache->reg_list;
/* load address into R1 */
regs[1] = address;
......@@ -280,7 +280,7 @@ static int arm920t_read_cp15_interpreted(struct target *target,
cp15_opcode, address, *value);
#endif
if (!is_arm_mode(armv4_5->core_mode))
if (!is_arm_mode(arm->core_mode))
{
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
......@@ -297,9 +297,9 @@ int arm920t_write_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
struct arm *armv4_5 = target_to_arm(target);
struct arm *arm = target_to_arm(target);
uint32_t regs[2];
struct reg *r = armv4_5->core_cache->reg_list;
struct reg *r = arm->core_cache->reg_list;
/* load value, address into R0, R1 */
regs[0] = value;
......@@ -325,7 +325,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
cp15_opcode, value, address);
#endif
if (!is_arm_mode(armv4_5->core_mode))
if (!is_arm_mode(arm->core_mode))
{
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
......@@ -763,7 +763,7 @@ int arm920t_soft_reset_halt(struct target *target)
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
......@@ -807,16 +807,16 @@ int arm920t_soft_reset_halt(struct target *target)
/* SVC, ARM state, IRQ and FIQ disabled */
uint32_t cpsr;
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(armv4_5, cpsr);
armv4_5->cpsr->dirty = 1;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm920t_disable_mmu_caches(target, 1, 1, 1);
arm920t->armv4_5_mmu.mmu_enabled = 0;
......@@ -841,8 +841,8 @@ static int arm920t_init_arch_info(struct target *target,
{
struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
arm7_9->armv4_5_common.mrc = arm920t_mrc;
arm7_9->armv4_5_common.mcr = arm920t_mcr;
arm7_9->arm.mrc = arm920t_mrc;
arm7_9->arm.mcr = arm920t_mcr;
/* initialize arm7/arm9 specific info (including armv4_5) */
arm9tdmi_init_arch_info(target, arm7_9, tap);
......@@ -887,7 +887,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
......@@ -1148,14 +1148,14 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
fclose(output);
if (!is_arm_mode(armv4_5->core_mode))
if (!is_arm_mode(arm->core_mode))
{
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
/* force writeback of the valid data */
r = armv4_5->core_cache->reg_list;
r = arm->core_cache->reg_list;
r[0].dirty = r[0].valid;
r[1].dirty = r[1].valid;
r[2].dirty = r[2].valid;
......@@ -1165,10 +1165,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
r[6].dirty = r[6].valid;
r[7].dirty = r[7].valid;
r = arm_reg_current(armv4_5, 8);
r = arm_reg_current(arm, 8);
r->dirty = r->valid;
r = arm_reg_current(armv4_5, 9);
r = arm_reg_current(arm, 9);
r->dirty = r->valid;
return ERROR_OK;
......@@ -1180,7 +1180,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
......@@ -1477,14 +1477,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
fclose(output);
if (!is_arm_mode(armv4_5->core_mode))
if (!is_arm_mode(arm->core_mode))
{
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
/* force writeback of the valid data */
r = armv4_5->core_cache->reg_list;
r = arm->core_cache->reg_list;
r[0].dirty = r[0].valid;
r[1].dirty = r[1].valid;
r[2].dirty = r[2].valid;
......@@ -1494,10 +1494,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
r[6].dirty = r[6].valid;
r[7].dirty = r[7].valid;
r = arm_reg_current(armv4_5, 8);
r = arm_reg_current(arm, 8);
r->dirty = r->valid;
r = arm_reg_current(armv4_5, 9);
r = arm_reg_current(arm, 9);
r->dirty = r->valid;
return ERROR_OK;
......
......@@ -42,7 +42,7 @@ static inline struct arm920t_common *
target_to_arm920(struct target *target)
{
return container_of(target->arch_info, struct arm920t_common,
arm7_9_common.armv4_5_common);
arm7_9_common.arm);
}
struct arm920t_cache_line
......
......@@ -557,7 +557,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
......@@ -600,16 +600,16 @@ int arm926ejs_soft_reset_halt(struct target *target)
/* SVC, ARM state, IRQ and FIQ disabled */
uint32_t cpsr;
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(armv4_5, cpsr);
armv4_5->cpsr->dirty = 1;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
......@@ -713,8 +713,8 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
{
struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
arm7_9->arm.mrc = arm926ejs_mrc;
arm7_9->arm.mcr = arm926ejs_mcr;
/* initialize arm7/arm9 specific info (including armv4_5) */
arm9tdmi_init_arch_info(target, arm7_9, tap);
......
......@@ -42,7 +42,7 @@ static inline struct arm926ejs_common *
target_to_arm926(struct target *target)
{
return container_of(target->arch_info, struct arm926ejs_common,
arm7_9_common.armv4_5_common);
arm7_9_common.arm);
}
......
......@@ -41,7 +41,7 @@ static inline struct arm946e_common *
target_to_arm946(struct target *target)
{
return container_of(target->arch_info, struct arm946e_common,
arm7_9_common.armv4_5_common);
arm7_9_common.arm);
}
int arm946e_init_arch_info(struct target *target,
......
......@@ -38,7 +38,7 @@ static inline struct arm966e_common *
target_to_arm966(struct target *target)
{
return container_of(target->arch_info, struct arm966e_common,
arm7_9_common.armv4_5_common);
arm7_9_common.arm);
}
int arm966e_init_arch_info(struct target *target,
......
......@@ -658,7 +658,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target)
LOG_DEBUG("-");
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct arm *arm = &arm7_9->arm;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
......@@ -673,7 +673,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP,
buf_get_u32(armv4_5->pc->value, 0, 32) | 1, NULL, 0);
buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0);
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
......@@ -700,7 +700,8 @@ static void arm9tdmi_branch_resume_thumb(struct target *target)
/* fetch NOP, LDR in Execute */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP,
buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
......@@ -746,9 +747,9 @@ void arm9tdmi_disable_single_step(struct target *target)
static void arm9tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
struct arm *arm = target_to_arm(target);
(*cache_p) = arm_build_reg_cache(target, armv4_5);
(*cache_p) = arm_build_reg_cache(target, arm);
}
int arm9tdmi_init_target(struct command_context *cmd_ctx,
......@@ -817,7 +818,7 @@ static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common));
arm9tdmi_init_arch_info(target, arm7_9, target->tap);
arm7_9->armv4_5_common.is_armv4 = true;
arm7_9->arm.is_armv4 = true;
return ERROR_OK;
}
......
......@@ -781,71 +781,71 @@ static int arm_simulate_step_core(struct target *target,
static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
return buf_get_u32(arm->core_cache->reg_list[reg].value, 0, 32);
}
static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
buf_set_u32(arm->core_cache->reg_list[reg].value, 0, 32, value);
}
static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32);
return buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm->core_mode, reg).value, 0, 32);
}
static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32, value);
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm->core_mode, reg).value, 0, 32, value);
}
static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
return buf_get_u32(armv4_5->cpsr->value, pos, bits);
return buf_get_u32(arm->cpsr->value, pos, bits);
}
static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
return armv4_5->core_state;
return arm->core_state;
}
static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
armv4_5->core_state = mode;
arm->core_state = mode;
}
static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
struct arm *arm = (struct arm *)sim->user_data;
return armv4_5->core_mode;
return arm->core_mode;
}
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
struct arm *armv4_5 = target_to_arm(target);
struct arm *arm = target_to_arm(target);
struct arm_sim_interface sim;
sim.user_data = armv4_5;
sim.user_data = arm;
sim.get_reg = &armv4_5_get_reg;
sim.set_reg = &armv4_5_set_reg;
sim.get_reg_mode = &armv4_5_get_reg_mode;
......
......@@ -470,8 +470,8 @@ static void arm_gdb_dummy_init(void)
static int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
struct arm_reg *reg_arch_info = reg->arch_info;
struct target *target = reg_arch_info->target;
if (target->state != TARGET_HALTED)
{
......@@ -479,7 +479,8 @@ static int armv4_5_get_core_reg(struct reg *reg)
return ERROR_TARGET_NOT_HALTED;
}
retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode);
retval = reg_arch_info->arm->read_core_reg(target, reg,
reg_arch_info->num, reg_arch_info->mode);
if (retval == ERROR_OK) {
reg->valid = 1;
reg->dirty = 0;
......@@ -490,8 +491,8 @@ static int armv4_5_get_core_reg(struct reg *reg)
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct arm_reg *armv4_5 = reg