Commit 38d053d1 authored by Leonard Crestez's avatar Leonard Crestez Committed by Matthias Welwarsky

target/imx6: Update list of supported TAPIDs

Copy all SJC TAPIPs from imx6 reference manuals.

Some imx6 chips are based on Cortex-A7 or have an additional Cortex-M4
and need separate scripts.

Change-Id: I3b07d94058c2c5e6313cfc8bb43134a90682a62e
Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Reviewed-on: http://openocd.zylin.com/5034
Tested-by: jenkins
Reviewed-by: default avatarMatthias Welwarsky <matthias@welwarsky.de>
parent 3b291a36
# Freescale i.MX6 series single/dual/quad core processor
#
# Freescale i.MX6 series
#
# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
#
# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
......@@ -20,19 +26,34 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
# List supported SJC TAPIDs from imx reference manuals:
set _SJC_TAPID_6Q 0x0191c01d
set _SJC_TAPID_6D 0x0191e01d
set _SJC_TAPID_6QP 0x3191c01d
set _SJC_TAPID_6DP 0x3191d01d
set _SJC_TAPID_6DL 0x0891a01d
set _SJC_TAPID_6S 0x0891b01d
set _SJC_TAPID_6SL 0x0891f01d
set _SJC_TAPID_6SLL 0x088c201d
# Allow external override of the first SJC TAPID
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0191c01d
set _SJC_TAPID $_SJC_TAPID_6Q
}
set _SJC_TAPID2 0x2191c01d
set _SJC_TAPID3 0x2191e01d
set _SJC_TAPID4 0x1191c01d
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-ignore-version \
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
-expected-id $_SJC_TAPID \
-expected-id $_SJC_TAPID_6QP \
-expected-id $_SJC_TAPID_6DP \
-expected-id $_SJC_TAPID_6D \
-expected-id $_SJC_TAPID_6DL \
-expected-id $_SJC_TAPID_6S \
-expected-id $_SJC_TAPID_6SL \
-expected-id $_SJC_TAPID_6SLL
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
......
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