Commit 2e779198 authored by zwelch's avatar zwelch
Browse files

Remove whitespace at end of lines, step 1.

- Replace '\s*$' with ''.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent c493543f
......@@ -109,10 +109,10 @@ static int aduc702x_flash_bank_command(struct command_context_s *cmd_ctx, char *
static int aduc702x_build_sector_list(struct flash_bank_s *bank)
{
//aduc7026_flash_bank_t *aduc7026_info = bank->driver_priv;
int i = 0;
uint32_t offset = 0;
// sector size is 512
bank->num_sectors = bank->size / 512;
bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
......@@ -203,7 +203,7 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
reg_param_t reg_params[6];
armv4_5_algorithm_t armv4_5_info;
int retval = ERROR_OK;
/* parameters:
r0 - address of source data (absolute)
......@@ -240,7 +240,7 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
//<done>:
0xeafffffe // b 1003c <done>
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
&aduc702x_info->write_algorithm) != ERROR_OK)
......@@ -248,8 +248,8 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
target_write_buffer(target, aduc702x_info->write_algorithm->address,
target_write_buffer(target, aduc702x_info->write_algorithm->address,
sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);
/* memory buffer */
......@@ -261,26 +261,26 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (aduc702x_info->write_algorithm)
target_free_working_area(target, aduc702x_info->write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
while (count > 0)
{
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
target_write_buffer(target, source->address, thisrun_count * 2, buffer);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
......@@ -288,16 +288,16 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
if ((retval = target_run_algorithm(target, 0, NULL, 5,
reg_params, aduc702x_info->write_algorithm->address,
aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
if ((retval = target_run_algorithm(target, 0, NULL, 5,
reg_params, aduc702x_info->write_algorithm->address,
aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
10000, &armv4_5_info)) != ERROR_OK)
{
LOG_ERROR("error executing aduc702x flash write algorithm");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
retval = ERROR_FLASH_OPERATION_FAILED;
break;
......@@ -310,24 +310,24 @@ static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint
target_free_working_area(target, source);
target_free_working_area(target, aduc702x_info->write_algorithm);
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]);
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
return retval;
}
/* All-JTAG, single-access method. Very slow. Used only if there is no
/* All-JTAG, single-access method. Very slow. Used only if there is no
* working area available. */
static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
uint32_t x;
uint8_t b;
target_t *target = bank->target;
aduc702x_set_write_enable(target, 1);
for (x = 0; x < count; x += 2) {
......@@ -373,13 +373,13 @@ int aduc702x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset,
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
* use normal (slow) JTAG method */
* use normal (slow) JTAG method */
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
if ((retval = aduc702x_write_single(bank, buffer, offset, count)) != ERROR_OK)
{
LOG_ERROR("slow write failed");
return ERROR_FLASH_OPERATION_FAILED;
return ERROR_FLASH_OPERATION_FAILED;
}
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
......
......@@ -57,7 +57,7 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
......@@ -85,8 +85,8 @@ static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","AR
static long SRAMSIZ[16] = {
-1,
0x0400, /* 1K */
0x0800, /* 2K */
-1,
0x0800, /* 2K */
-1,
0x1c000, /* 112K */
0x1000, /* 4K */
0x14000, /* 80K */
......@@ -135,10 +135,10 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
target_read_u32(target, PMC_MCKR, &mckr);
/* Read Clock Generator PLL Register */
target_read_u32(target, CKGR_PLLR, &pllr);
at91sam7_info->mck_valid = 0;
at91sam7_info->mck_freq = 0;
switch (mckr & PMC_MCKR_CSS)
switch (mckr & PMC_MCKR_CSS)
{
case 0: /* Slow Clock */
at91sam7_info->mck_valid = 1;
......@@ -146,7 +146,7 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
break;
case 1: /* Main Clock */
if ((mcfr & CKGR_MCFR_MAINRDY) &&
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
at91sam7_info->mck_valid = 1;
......@@ -163,8 +163,8 @@ static void at91sam7_read_clock_info(flash_bank_t *bank)
break;
case 3: /* PLL Clock */
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
if ((mcfr & CKGR_MCFR_MAINRDY) &&
(at91sam7_info->ext_freq == 0))
{
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
......@@ -280,7 +280,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
......@@ -294,7 +294,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
return ERROR_OK;
}
if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
{
return ERROR_FLASH_OPERATION_FAILED;
}
......@@ -635,7 +635,7 @@ static int at91sam7_erase_check(struct flash_bank_s *bank)
}
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
fast_check = 1;
......@@ -892,7 +892,7 @@ static int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
if (erase_all)
{
if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
}
......@@ -1079,13 +1079,13 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
buf += printed;
buf_size -= printed;
printed = snprintf(buf,
printed = snprintf(buf,
buf_size,
" Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
at91sam7_info->cidr,
at91sam7_info->cidr_arch,
at91sam7_info->cidr,
at91sam7_info->cidr_arch,
EPROC[at91sam7_info->cidr_eproc],
at91sam7_info->cidr_version,
at91sam7_info->cidr_version,
bank->size);
buf += printed;
......@@ -1117,10 +1117,10 @@ static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
return ERROR_OK;
}
/*
* On AT91SAM7S: When the gpnvm bits are set with
/*
* On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm bitnr set
* the changes are not visible in the flash controller status register MC_FSR
* the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset.
* On the Olimex board this requires a power cycle.
* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
......@@ -1191,7 +1191,7 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
{
return ERROR_FLASH_OPERATION_FAILED;
......@@ -1203,6 +1203,6 @@ static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char
/* check protect state */
at91sam7_protect_check(bank);
return ERROR_OK;
}
......@@ -378,9 +378,9 @@ static int cfi_read_intel_pri_ext(flash_bank_t *bank)
pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
pri_ext->feature_support,
pri_ext->suspend_cmd_support,
pri_ext->blk_status_reg_mask);
pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
......@@ -1597,7 +1597,7 @@ static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint3
/* Check for valid range */
if (address & buffermask)
{
LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
......@@ -2279,9 +2279,9 @@ static int cfi_probe(struct flash_bank_s *bank)
for (i = 0; i < cfi_info->num_erase_regions; i++)
{
cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
(cfi_info->erase_region_info[i] >> 16) * 256);
}
}
......
......@@ -92,7 +92,7 @@ static int flash_driver_write(struct flash_bank_s *bank, uint8_t *buffer, uint32
retval = bank->driver->write(bank, buffer, offset, count);
if (retval != ERROR_OK)
{
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
bank->base, offset, retval);
}
......@@ -350,13 +350,13 @@ static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cm
if ((retval = p->driver->auto_probe(p)) != ERROR_OK)
return retval;
command_print(cmd_ctx,
command_print(cmd_ctx,
"#%" PRIi32 " : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", buswidth %i, chipwidth %i",
i,
p->driver->name,
p->base,
p->size,
p->bus_width,
p->driver->name,
p->base,
p->size,
p->bus_width,
p->chip_width);
for (j = 0; j < p->num_sectors; j++)
{
......@@ -369,11 +369,11 @@ static int handle_flash_info_command(struct command_context_s *cmd_ctx, char *cm
else
protect_state = "protection state unknown";
command_print(cmd_ctx,
command_print(cmd_ctx,
"\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
j,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].size >> 10,
protect_state);
}
......@@ -462,9 +462,9 @@ static int handle_flash_erase_check_command(struct command_context_s *cmd_ctx, c
command_print(cmd_ctx,
"\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
j,
p->sectors[j].offset,
p->sectors[j].size,
j,
p->sectors[j].offset,
p->sectors[j].size,
p->sectors[j].size >> 10,
erase_state);
}
......@@ -708,10 +708,10 @@ static int handle_flash_write_image_command(struct command_context_s *cmd_ctx, c
}
if (retval == ERROR_OK)
{
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %" PRIu32 " byte from file %s in %s (%f kb/s)",
written,
args[0],
args[0],
duration_text,
(float)written / 1024.0 / ((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0)));
}
......@@ -813,7 +813,7 @@ static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cm
{
if (readback[i]!=chunk[i])
{
LOG_ERROR("Verfication error address 0x%08" PRIx32 ", read back 0x%02x, expected 0x%02x",
LOG_ERROR("Verfication error address 0x%08" PRIx32 ", read back 0x%02x, expected 0x%02x",
address + wrote + i, readback[i], chunk[i]);
return ERROR_FAIL;
}
......@@ -831,10 +831,10 @@ static int handle_flash_fill_command(struct command_context_s *cmd_ctx, char *cm
float speed;
speed = wrote / 1024.0;
speed/=((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0));
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %" PRId32 " bytes to 0x%8.8" PRIx32 " in %s (%f kb/s)",
count*wordsize,
address,
count*wordsize,
address,
duration_text,
speed);
}
......@@ -896,12 +896,12 @@ static int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, ch
}
if (retval == ERROR_OK)
{
command_print(cmd_ctx,
command_print(cmd_ctx,
"wrote %lld byte from file %s to flash bank %li at offset 0x%8.8" PRIx32 " in %s (%f kb/s)",
fileio.size,
args[1],
strtoul(args[0], NULL, 0),
offset,
fileio.size,
args[1],
strtoul(args[0], NULL, 0),
offset,
duration_text,
(float)fileio.size / 1024.0 / ((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0)));
}
......
......@@ -81,13 +81,13 @@ struct flash_bank_s;
*/
typedef struct flash_driver_s
{
/**
/**
* Gives a human-readable name of this flash driver,
* This field is used to select and initialize the driver.
*/
char *name;
/**
/**
* Registers driver-specific commands. When called (during the
* "flash bank" command), the driver may register addition
* commands to support new flash chip functions.
......@@ -96,12 +96,12 @@ typedef struct flash_driver_s
*/
int (*register_commands)(struct command_context_s *cmd_ctx);
/**
/**
* Finish the "flash bank" command for @a bank. The
* @a bank parameter will have been filled in by the core flash
* layer when this routine is called, and the driver can store
* additional information in its flash_bank_t::driver_priv field.
*
*
* @param cmd_ctx - the command context
* @param cmd - the command, in this case 'flash'
* @param args - parameters, see below
......@@ -112,7 +112,7 @@ typedef struct flash_driver_s
* @code
* args[0] = bank
* args[1] = drivername {name above}
* args[2] = baseaddress
* args[2] = baseaddress
* args[3] = lengthbytes
* args[4] = chip_width_in bytes
* args[5] = bus_width_bytes
......@@ -129,7 +129,7 @@ typedef struct flash_driver_s
*/
int (*flash_bank_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
/**
/**
* Bank/sector erase routine (target-specific). When
* called, the flash driver should erase the specified sectors
* using whatever means are at its disposal.
......@@ -141,7 +141,7 @@ typedef struct flash_driver_s
*/
int (*erase)(struct flash_bank_s *bank, int first, int last);
/**
/**
* Bank/sector protection routine (target-specific).
* When called, the driver should disable 'flash write' bits (or
* enable 'erase protection' bits) for the given @a bank and @a
......@@ -155,7 +155,7 @@ typedef struct flash_driver_s
*/
int (*protect)(struct flash_bank_s *bank, int set, int first, int last);
/**
/**
* Program data into the flash. Note CPU address will be
* "bank->base + offset", while the physical address is
* dependent upon current target MMU mappings.
......@@ -168,7 +168,7 @@ typedef struct flash_driver_s
*/
int (*write)(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
/**
/**
* Probe to determine what kind of flash is present.
* This is invoked by the "probe" script command.
*
......@@ -176,8 +176,8 @@ typedef struct flash_driver_s
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int (*probe)(struct flash_bank_s *bank);
/**
/**
* Check the erasure status of a flash bank.
* When called, the driver routine must perform the required
* checks and then set the @c flash_sector_s::is_erased field
......@@ -209,7 +209,7 @@ typedef struct flash_driver_s
* @param char - where to put the text for the human to read
* @param buf_size - the size of the human buffer.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
*/
int (*info)(struct flash_bank_s *bank, char *buf, int buf_size);
/**
......@@ -228,7 +228,7 @@ typedef struct flash_driver_s
int (*auto_probe)(struct flash_bank_s *bank);
} flash_driver_t;
/**
/**
* Provides details of a flash bank, available either on-chip or through
* a major interface.
*
......@@ -276,7 +276,7 @@ extern int flash_init_drivers(struct command_context_s *cmd_ctx);
extern int flash_erase_address_range(struct target_s *target, uint32_t addr, uint32_t length);
/**
* Writes @a image into the @a target flash. The @a written parameter
* will contain the
* will contain the
* @param target The target with the flash to be programmed.
* @param image The image that will be programmed to flash.
* @param written On return, contains the number of bytes written.
......
......@@ -474,7 +474,7 @@ static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : 0x%0lx", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : 0x%0lx", sect_num,
(unsigned long)buff_ptr);
ret = mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
if (ret != ERROR_OK)
......@@ -485,7 +485,7 @@ static int mg_mflash_read_sects(void *buff, uint32_t sect_num, uint32_t sect_cnt
}
if (residue) {
LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %0lx", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIx32 " buff : %0lx", sect_num,
(unsigned long)buff_ptr);
return mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
}
......@@ -517,7 +517,7 @@ static int mg_mflash_do_write_sects(void *buff, uint32_t sect_num, uint32_t sect
ret = target_write_memory(target, address, 2, MG_MFLASH_SECTOR_SIZE / 2, buff_ptr);
if (ret != ERROR_OK)
return ret;
buff_ptr += MG_MFLASH_SECTOR_SIZE;
ret = target_write_u8(target, mflash_bank->base + MG_REG_OFFSET + MG_REG_COMMAND, mg_io_cmd_confirm_write);
......@@ -552,7 +552,7 @@ static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cn
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 "buff : %p", sect_num,
buff_ptr);
ret = mg_mflash_do_write_sects(buff_ptr, sect_num, 256, mg_io_cmd_write);
if (ret != ERROR_OK)
......@@ -563,7 +563,7 @@ static int mg_mflash_write_sects(void *buff, uint32_t sect_num, uint32_t sect_cn
}
if (residue) {
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
LOG_DEBUG("mflash: sect num : %" PRIu32 " buff : %p", sect_num,
buff_ptr);
return mg_mflash_do_write_sects(buff_ptr, sect_num, residue, mg_io_cmd_write);
}
......@@ -741,10 +741,10 @@ static int mg_write_cmd(struct command_context_s *cmd_ctx, char *cmd, char **arg
goto mg_write_cmd_err;
address += MG_FILEIO_CHUNK;
}
if (res) {
if ((ret = fileio_read(&fileio, res, buffer, &buf_cnt)) != ERROR_OK)
goto mg_write_cmd_err;
goto mg_write_cmd_err;
if ((ret = mg_mflash_write(address, buffer, res)) != ERROR_OK)
goto mg_write_cmd_err;
}
......@@ -789,7 +789,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
ret = fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY);
if (ret != ERROR_OK)
return ret;
buffer = malloc(MG_FILEIO_CHUNK);
if (!buffer) {
fileio_close(&fileio);
......@@ -798,7 +798,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
cnt = size / MG_FILEIO_CHUNK;
res = size % MG_FILEIO_CHUNK;
duration_start_measure(&duration);
for (i = 0; i < cnt; i++) {
......@@ -809,7 +809,7 @@ static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args
goto mg_dump_cmd_err;
address += MG_FILEIO_CHUNK;
}
if (res) {
if ((ret = mg_mflash_read(address, buffer, res)) != ERROR_OK)
goto mg_dump_cmd_err;
......@@ -834,8 +834,8 @@ mg_dump_cmd_err:
free(duration_text);
free(buffer);
fileio_close(&fileio);
return ret;
return ret;
}
static int mg_set_feature(mg_feature_id feature, mg_feature_val config)
......@@ -1229,7 +1229,7 @@ int mg_config_cmd(struct command_context_s *cmd_ctx, char *cmd,
switch (argc) {
case 2:
if (!strcmp(args[1], "boot"))
if (!strcmp(args[1], "boot"))
return mg_boot_config();
else if (!strcmp(args[1], "storage"))
return mg_storage_config();
......@@ -1252,7 +1252,7 @@ int mg_config_cmd(struct command_context_s *cmd_ctx, char *cmd,
return ERROR_MG_INVALID_PLL;
}
LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
LOG_INFO("mflash: Fout=%" PRIu32 " Hz, feedback=%u,"
"indiv=%u, outdiv=%u, lock=%u",
(uint32_t)fout, pll.feedback_div,
pll.input_div, pll.output_div,
......