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card10
openocd
Commits
290d00e6
Commit
290d00e6
authored
Mar 01, 2008
by
mifi
Browse files
- added example for testing the JTAG speed with a FT2232 device
git-svn-id:
svn://svn.berlios.de/openocd/trunk@422
b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent
2ce5ca9f
Changes
7
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testing/examples/STR710JtagSpeed/inc/typedefs.h
0 → 100644
View file @
290d00e6
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
* History:
*
* 30.03.06 mifi First Version for Insight tutorial
****************************************************************************/
#ifndef __TYPEDEFS_H__
#define __TYPEDEFS_H__
/*
* Some types to use Windows like source
*/
typedef
char
CHAR
;
/* 8-bit signed data */
typedef
unsigned
char
BYTE
;
/* 8-bit unsigned data */
typedef
unsigned
short
WORD
;
/* 16-bit unsigned data */
typedef
long
LONG
;
/* 32-bit signed data */
typedef
unsigned
long
ULONG
;
/* 32-bit unsigned data */
typedef
unsigned
long
DWORD
;
/* 32-bit unsigned data */
#endif
/* !__TYPEDEFS_H_ */
/*** EOF ***/
testing/examples/STR710JtagSpeed/makefile
0 → 100644
View file @
290d00e6
#
# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!!
#
##############################################################################################
#
# On command line:
#
# make all = Create project
#
# make clean = Clean project files.
#
# To rebuild project do "make clean" and "make all".
#
##############################################################################################
# Start of default section
#
TRGT
=
arm-elf-
CC
=
$(TRGT)
gcc
CP
=
$(TRGT)
objcopy
AS
=
$(TRGT)
gcc
-x
assembler-with-cpp
BIN
=
$(CP)
-O
ihex
MCU
=
arm7tdmi
# List all default C defines here, like -D_DEBUG=1
DDEFS
=
# List all default ASM defines here, like -D_DEBUG=1
DADEFS
=
# List all default directories to look for include files here
DINCDIR
=
# List the default directory to look for the libraries here
DLIBDIR
=
# List all default libraries here
DLIBS
=
#
# End of default section
##############################################################################################
##############################################################################################
# Start of user section
#
# Define project name here
PROJECT
=
test
# Define linker script file here
LDSCRIPT
=
./prj/str7_ram.ld
# List all user C define here, like -D_DEBUG=1
UDEFS
=
# Define ASM defines here
UADEFS
=
# List C source files here
SRC
=
./src/main.c
# List ASM source files here
ASRC
=
./src/crt.s
# List all user directories here
UINCDIR
=
./inc
# List the user directory to look for the libraries here
ULIBDIR
=
# List all user libraries here
ULIBS
=
# Define optimisation level here
OPT
=
-O0
#
# End of user defines
##############################################################################################
INCDIR
=
$(
patsubst
%,-I%,
$(DINCDIR)
$(UINCDIR)
)
LIBDIR
=
$(
patsubst
%,-L%,
$(DLIBDIR)
$(ULIBDIR)
)
DEFS
=
$(DDEFS)
$(UDEFS)
ADEFS
=
$(DADEFS)
$(UADEFS)
OBJS
=
$(ASRC:.s=.o)
$(SRC:.c=.o)
LIBS
=
$(DLIBS)
$(ULIBS)
MCFLAGS
=
-mcpu
=
$(MCU)
ASFLAGS
=
$(MCFLAGS)
-g
-gdwarf-2
-Wa
,-amhls
=
$
(
<:.s
=
.lst
)
$(ADEFS)
CPFLAGS
=
$(MCFLAGS)
$(OPT)
-gdwarf-2
-mthumb-interwork
-fomit-frame-pointer
-Wall
-Wstrict-prototypes
-fverbose-asm
-Wa
,-ahlms
=
$
(
<:.c
=
.lst
)
$(DEFS)
LDFLAGS
=
$(MCFLAGS)
-nostartfiles
-T
$(LDSCRIPT)
-Wl
,-Map
=
$(PROJECT)
.map,--cref,--no-warn-mismatch
$(LIBDIR)
# Generate dependency information
CPFLAGS
+=
-MD
-MP
-MF
.dep/
$
(
@F
)
.d
#
# makefile rules
#
all
:
$(OBJS) $(PROJECT).elf $(PROJECT).hex
%o
:
%c
$(CC)
-c
$(CPFLAGS)
-I
.
$(INCDIR)
$<
-o
$@
%o
:
%s
$(AS)
-c
$(ASFLAGS)
$<
-o
$@
%elf
:
$(OBJS)
$(CC)
$(OBJS)
$(LDFLAGS)
$(LIBS)
-o
$@
%hex
:
%elf
$(BIN)
$<
$@
clean
:
-
rm
-f
$(OBJS)
-
rm
-f
$(PROJECT)
.elf
-
rm
-f
$(PROJECT)
.map
-
rm
-f
$(PROJECT)
.hex
-
rm
-f
$(SRC:.c=.c.bak)
-
rm
-f
$(SRC:.c=.lst)
-
rm
-f
$(ASRC:.s=.s.bak)
-
rm
-f
$(ASRC:.s=.lst)
-
rm
-fR
.dep
#
# Include the dependency files, should be the last of the makefile
#
-include
$(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
#
***
EOF
***
\ No newline at end of file
testing/examples/STR710JtagSpeed/prj/eclipse_ft2232_ram.gdb
0 → 100644
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290d00e6
target remote localhost:3333
monitor reset
monitor sleep 500
monitor poll
monitor soft_reset_halt
monitor arm7_9 sw_bkpts enable
monitor mww 0xA0000050 0x01c2
monitor mdw 0xA0000050
monitor mww 0x6C000004 0x8005
monitor mdw 0x6C000004
monitor mww 0xE0005000 0xFFFF
monitor mww 0xE0005004 0x00FF
monitor mww 0xE0005008 0xFFFF
monitor mdw 0xE0005000
monitor mdw 0xE0005004
monitor mdw 0xE0005008
monitor mww 0xE000500C 0x0000
monitor arm7_9 fast_memory_access enable
monitor arm7_9 dcc_downloads enable
monitor verify_ircapture disable
load
break main
continue
testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg
0 → 100644
View file @
290d00e6
#daemon configuration
telnet_port 4444
gdb_port 3333
# tell gdb our flash memory map
# and enable flash programming
gdb_memory_map enable
gdb_flash_program enable
#interface
interface ft2232
ft2232_device_desc "Amontec JTAGkey A"
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0xcff8
jtag_speed 0
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe
#target configuration
daemon_startup reset
#target <type> <startup mode>
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
target arm7tdmi little run_and_halt 0 arm7tdmi
run_and_halt_time 0 30
working_area 0 0x2000C000 0x4000 nobackup
#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
# For more information about the configuration files, take a look at:
# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
testing/examples/STR710JtagSpeed/prj/str7_ram.ld
0 → 100644
View file @
290d00e6
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 30.03.06 mifi First Version
****************************************************************************/
ENTRY(ResetHandler)
SEARCH_DIR(.)
/*
* Define stack size here
*/
FIQ_STACK_SIZE = 0x0100;
IRQ_STACK_SIZE = 0x0100;
ABT_STACK_SIZE = 0x0100;
UND_STACK_SIZE = 0x0100;
SVC_STACK_SIZE = 0x0400;
/*
* This file, hitex_str7_ram.ld, locate the program in the internal
* ram of the STR7. For more information about the memory of the STR7
* take a look in the STR71X Microcontroller Reference Manual.
* Reference is made to Rev. 6 March 2005
*
* Take a look at page 16, section 2.1.1 Memory Map
*/
MEMORY
{
ram : org = 0x62000000, len = 512k
}
/*
* Do not change the next code
*/
SECTIONS
{
.text :
{
*(.vectors);
. = ALIGN(4);
*(.init);
. = ALIGN(4);
*(.text);
. = ALIGN(4);
*(.rodata);
. = ALIGN(4);
*(.rodata*);
. = ALIGN(4);
*(.glue_7t);
. = ALIGN(4);
*(.glue_7);
. = ALIGN(4);
etext = .;
} > ram
.data :
{
PROVIDE (__data_start = .);
*(.data)
. = ALIGN(4);
edata = .;
_edata = .;
PROVIDE (__data_end = .);
} > ram
.bss :
{
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
. = ALIGN(256);
PROVIDE (__stack_start = .);
PROVIDE (__stack_fiq_start = .);
. += FIQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_fiq_end = .);
PROVIDE (__stack_irq_start = .);
. += IRQ_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_irq_end = .);
PROVIDE (__stack_abt_start = .);
. += ABT_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_abt_end = .);
PROVIDE (__stack_und_start = .);
. += UND_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_und_end = .);
PROVIDE (__stack_svc_start = .);
. += SVC_STACK_SIZE;
. = ALIGN(4);
PROVIDE (__stack_svc_end = .);
PROVIDE (__stack_end = .);
PROVIDE (__heap_start = .);
} > ram
}
/*** EOF ***/
testing/examples/STR710JtagSpeed/src/crt.s
0 → 100644
View file @
290d00e6
/****************************************************************************
*
Copyright
(
c
)
2006
by
Michael
Fischer
.
All
rights
reserved
.
*
*
Redistribution
and
use
in
source
and
binary
forms
,
with
or
without
*
modification
,
are
permitted
provided
that
the
following
conditions
*
are
met
:
*
*
1.
Redistributions
of
source
code
must
retain
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
.
*
2.
Redistributions
in
binary
form
must
reproduce
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
in
the
*
documentation
and
/
or
other
materials
provided
with
the
distribution
.
*
3.
Neither
the
name
of
the
author
nor
the
names
of
its
contributors
may
*
be
used
to
endorse
or
promote
products
derived
from
this
software
*
without
specific
prior
written
permission
.
*
*
THIS
SOFTWARE
IS
PROVIDED
BY
THE
COPYRIGHT
HOLDERS
AND
CONTRIBUTORS
*
"
AS
IS
" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*
LIMITED
TO
,
THE
IMPLIED
WARRANTIES
OF
MERCHANTABILITY
AND
FITNESS
*
FOR
A
PARTICULAR
PURPOSE
ARE
DISCLAIMED
.
IN
NO
EVENT
SHALL
*
THE
COPYRIGHT
OWNER
OR
CONTRIBUTORS
BE
LIABLE
FOR
ANY
DIRECT
,
INDIRECT
,
*
INCIDENTAL
,
SPECIAL
,
EXEMPLARY
,
OR
CONSEQUENTIAL
DAMAGES
(
INCLUDING
,
*
BUT
NOT
LIMITED
TO
,
PROCUREMENT
OF
SUBSTITUTE
GOODS
OR
SERVICES
; LOSS
*
OF
USE
,
DATA
,
OR
PROFITS
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
*
AND
ON
ANY
THEORY
OF
LIABILITY
,
WHETHER
IN
CONTRACT
,
STRICT
LIABILITY
,
*
OR
TORT
(
INCLUDING
NEGLIGENCE
OR
OTHERWISE
)
ARISING
IN
ANY
WAY
OUT
OF
*
THE
USE
OF
THIS
SOFTWARE
,
EVEN
IF
ADVISED
OF
THE
POSSIBILITY
OF
*
SUCH
DAMAGE
.
*
****************************************************************************
*
*
History
:
*
*
04.03.06
mifi
First
Version
*
This
version
based
on
an
example
from
Ethernut
and
*
"
ARM
Cross
Development
with
Eclipse
" from James P. Lynch
****************************************************************************/
/*
*
Some
defines
for
the
program
status
registers
*/
ARM_MODE_USER
=
0x10
/*
Normal
User
Mode
*/
ARM_MODE_FIQ
=
0x11
/*
FIQ
Fast
Interrupts
Mode
*/
ARM_MODE_IRQ
=
0x12
/*
IRQ
Standard
Interrupts
Mode
*/
ARM_MODE_SVC
=
0x13
/*
Supervisor
Interrupts
Mode
*/
ARM_MODE_ABORT
=
0x17
/*
Abort
Processing
memory
Faults
Mode
*/
ARM_MODE_UNDEF
=
0x1B
/*
Undefined
Instructions
Mode
*/
ARM_MODE_SYS
=
0x1F
/*
System
Running
in
Priviledged
Operating
Mode
*/
ARM_MODE_MASK
=
0x1F
I_BIT
=
0x80
/*
disable
IRQ
when
I
bit
is
set
*/
F_BIT
=
0x40
/*
disable
IRQ
when
I
bit
is
set
*/
/*
*
Register
Base
Address
*/
PRCCU_BASE
=
0xA0000000
RCCU_CFR
=
0x08
RCCU_PLL1CR
=
0x18
PCU_MDIVR
=
0x40
PCU_PDIVR
=
0x44
PCU_BOOTCR
=
0x50
.
section
.
vectors
,
"ax"
.
code
32
/****************************************************************************/
/*
Vector
table
and
reset
entry
*/
/****************************************************************************/
_vectors
:
ldr
pc
,
ResetAddr
/*
Reset
*/
ldr
pc
,
UndefAddr
/*
Undefined
instruction
*/
ldr
pc
,
SWIAddr
/*
Software
interrupt
*/
ldr
pc
,
PAbortAddr
/*
Prefetch
abort
*/
ldr
pc
,
DAbortAddr
/*
Data
abort
*/
ldr
pc
,
ReservedAddr
/*
Reserved
*/
ldr
pc
,
IRQAddr
/*
IRQ
interrupt
*/
ldr
pc
,
FIQAddr
/*
FIQ
interrupt
*/
ResetAddr
:
.
word
ResetHandler
UndefAddr
:
.
word
UndefHandler
SWIAddr
:
.
word
SWIHandler
PAbortAddr
:
.
word
PAbortHandler
DAbortAddr
:
.
word
DAbortHandler
ReservedAddr
:
.
word
0
IRQAddr
:
.
word
IRQHandler
FIQAddr
:
.
word
FIQHandler
.
ltorg
.
section
.
init
,
"ax"
.
code
32
.
global
ResetHandler
.
global
ExitFunction
.
extern
main
/****************************************************************************/
/*
Reset
handler
*/
/****************************************************************************/
ResetHandler
:
/*
*
Wait
for
the
oscillator
is
stable
*/
nop
nop
nop
nop
nop
nop
nop
nop
/*
*
Setup
STR71X
,
for
more
information
about
the
register
*
take
a
look
in
the
STR71x
Microcontroller
Reference
Manual
.
*
*
Reference
is
made
to
:
Rev
.
6
March
2005
*
*
1
.
Map
internal
RAM
to
address
0
*
In
this
case
,
we
are
running
always
in
the
RAM
*
this
make
no
sence
.
But
if
we
are
in
flash
,
we
*
can
copy
the
interrupt
vectors
into
the
ram
and
*
switch
to
RAM
mode
.
*
*
2
.
Setup
the
PLL
,
the
eval
board
HITEX
STR7
is
equipped
*
with
an
external
16
MHz
oscillator
.
We
want
:
*
*
RCLK
:
32
MHz
=
(
CLK2
*
16
)
/
4
*
MCLK
:
32
Mhz
*
PCLK1
:
32
MHz
*
PCLK2
:
32
MHz
*
*/
/
*
*
1
.
Map
RAM
to
the
boot
memory
0x00000000
*/
ldr
r0
,
=
PRCCU_BASE
ldr
r1
,
=
0x01C2
str
r1
,
[
r0
,
#
PCU_BOOTCR
]
/
*
*
2
.
Setup
PLL
start
*/
/
*
Set
the
prescaling
factor
for
APB
and
APB1
group
*/
ldr
r0
,
=
PRCCU_BASE
ldr
r1
,
=
0x0000
/*
no
prescaling
PCLKx
=
RCLK
*/
str
r1
,
[
r0
,
#
PCU_PDIVR
]
/
*
Set
the
prescaling
factor
for
the
Main
System
Clock
MCLK
*/
ldr
r0
,
=
PRCCU_BASE
ldr
r1
,
=
0x0000
/*
no
prescaling
MCLK
=
RCLK
str
r1
,
[
r0
,
#
PCU_MDIVR
]
/
*
Configure
the
PLL1
(
*
16
,
/
4
)
*/
ldr
r0
,
=
PRCCU_BASE
ldr
r1
,
=
0x0073
str
r1
,
[
r0
,
#
RCCU_PLL1CR
]
/
*
Check
if
the
PLL
is
locked
*/
pll_lock_loop
:
ldr
r1
,
[
r0
,
#
RCCU_CFR
]
tst
r1
,
#
0x0002
beq
pll_lock_loop
/
*
Select
PLL1_Output
as
RCLK
clock
*/
ldr
r0
,
=
PRCCU_BASE
ldr
r1
,
=
0x8009
str
r1
,
[
r0
,
#
RCCU_CFR
]
/
*
*
Setup
PLL
end
*/
/
*
*
Setup
a
stack
for
each
mode
*/
msr
CPSR_c
,
#
ARM_MODE_UNDEF
| I_BIT |
F_BIT
/*
Undefined
Instruction
Mode
*/
ldr
sp
,
=
__stack_und_end
msr
CPSR_c
,
#
ARM_MODE_ABORT
| I_BIT |
F_BIT
/*
Abort
Mode
*/
ldr
sp
,
=
__stack_abt_end
msr
CPSR_c
,
#
ARM_MODE_FIQ
| I_BIT |
F_BIT
/*
FIQ
Mode
*/
ldr
sp
,
=
__stack_fiq_end
msr
CPSR_c
,
#
ARM_MODE_IRQ
| I_BIT |
F_BIT
/*
IRQ
Mode
*/
ldr
sp
,
=
__stack_irq_end
msr
CPSR_c
,
#
ARM_MODE_SVC
| I_BIT |
F_BIT
/*
Supervisor
Mode
*/
ldr
sp
,
=
__stack_svc_end
/
*
*
Clear
.
bss
section
*/
ldr
r1
,
=
__bss_start
ldr
r2
,
=
__bss_end
ldr
r3
,
=
0
bss_clear_loop
:
cmp
r1
,
r2
strne
r3
,
[
r1
],
#+
4
bne
bss_clear_loop