Commit 257d238e authored by oharboe's avatar oharboe
Browse files

Laurentiu Cocanu - add error handling

git-svn-id: svn://svn.berlios.de/openocd/trunk@1057 b42882b7-edfa-0310-969c-e2dbd0fdcd60
parent 50959e13
......@@ -709,6 +709,8 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
/* target execution control */
int arm11_halt(struct target_s *target)
{
int retval = ERROR_OK;
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
......@@ -735,7 +737,10 @@ int arm11_halt(struct target_s *target)
arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
u32 dscr;
......@@ -754,14 +759,19 @@ int arm11_halt(struct target_s *target)
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
if((retval = target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
int retval = ERROR_OK;
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
......@@ -833,7 +843,10 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
while (1)
{
......@@ -847,15 +860,21 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
if (!debug_execution)
{
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
return retval;
}
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
return retval;
}
}
return ERROR_OK;
......@@ -863,6 +882,8 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
int retval = ERROR_OK;
FNC_INFO;
LOG_DEBUG("target->state: %s",
......@@ -937,7 +958,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
/** \todo TODO: add a timeout */
......@@ -964,7 +988,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
return ERROR_OK;
}
......@@ -1411,9 +1438,17 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
goto restore;
}
target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
// no debug, otherwise breakpoint is not set
if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
{
return retval;
}
if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
return retval;
}
target_wait_state(target, TARGET_HALTED, timeout_ms);
if (target->state != TARGET_HALTED)
{
if ((retval=target_halt(target))!=ERROR_OK)
......@@ -1483,6 +1518,7 @@ restore:
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
......@@ -1493,7 +1529,10 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp)
arm11->jtag_info.chain_pos = target->chain_position;
arm11->jtag_info.scann_size = 5;
arm_jtag_setup_connection(&arm11->jtag_info);
if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
{
return retval;
}
jtag_device_t *device = jtag_get_device(target->chain_position);
......
......@@ -89,6 +89,7 @@ target_type_t arm720t_target =
int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
......@@ -99,8 +100,14 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
{
return retval;
}
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 1;
......@@ -135,7 +142,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
jtag_add_runtest(0, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
......@@ -363,13 +373,17 @@ int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
int arm720t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
target_halt(target);
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
long long then=timeval_ms();
int timeout;
......@@ -378,7 +392,10 @@ int arm720t_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
} else
{
break;
......@@ -417,7 +434,10 @@ int arm720t_soft_reset_halt(struct target_s *target)
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
return ERROR_OK;
}
......@@ -531,7 +551,11 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
return ERROR_OK;
}
jtag_execute_queue();
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
}
......
This diff is collapsed.
......@@ -97,6 +97,7 @@ target_type_t arm7tdmi_target =
int arm7tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
......@@ -131,11 +132,17 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
arm_jtag_scann(&arm7_9->jtag_info, 0x1);
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, TAP_PD);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
fields[0].in_value = NULL;
fields[0].out_value = &breakpoint;
......@@ -182,10 +189,14 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr
/* clock the target, reading the databus */
int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
......@@ -214,7 +225,10 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
if (in)
{
......@@ -236,10 +250,14 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
*/
int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
......@@ -279,7 +297,10 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
if (in)
{
......@@ -851,6 +872,6 @@ int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
retval = arm7_9_register_commands(cmd_ctx);
return ERROR_OK;
return retval;
}
......@@ -625,13 +625,17 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
int arm920t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
target_halt(target);
if((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
long long then=timeval_ms();
int timeout;
......@@ -640,7 +644,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
} else
{
break;
......@@ -680,7 +687,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
}
return ERROR_OK;
}
......@@ -770,11 +780,12 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
return ERROR_OK;
return retval;
}
int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
......@@ -816,7 +827,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
cp15_ctrl_saved = cp15_ctrl;
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
......@@ -876,7 +890,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* read D RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
d_cache[segment][index].cam = regs[9];
......@@ -959,7 +976,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
/* read I RAM and CAM content */
arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
i_cache[segment][index].cam = regs[9];
......@@ -1019,6 +1039,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
......@@ -1060,14 +1081,20 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
cp15_ctrl_saved = cp15_ctrl;
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
/* read CP15 test state register */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
/* prepare reading D TLB content
* */
......@@ -1085,7 +1112,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
Dlockdown = regs[1];
for (victim = 0; victim < 64; victim += 8)
......@@ -1111,7 +1141,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
for (i = 0; i < 8; i++)
d_tlb[victim + i].cam = regs[i + 2];
......@@ -1143,7 +1176,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read D TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
d_tlb[victim].ram1 = regs[2];
d_tlb[victim].ram2 = regs[3];
......@@ -1172,7 +1208,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
Ilockdown = regs[1];
for (victim = 0; victim < 64; victim += 8)
......@@ -1198,7 +1237,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
for (i = 0; i < 8; i++)
i_tlb[i + victim].cam = regs[i + 2];
......@@ -1230,7 +1272,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
/* read I TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
i_tlb[victim].ram1 = regs[2];
i_tlb[victim].ram2 = regs[3];
......@@ -1317,7 +1362,10 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "couldn't access reg %i", address);
return ERROR_OK;
}
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
command_print(cmd_ctx, "%i: %8.8x", address, value);
}
......
......@@ -120,6 +120,7 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
......@@ -132,7 +133,10 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
buf_set_u32(address_buf, 0, 14, address);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0xf);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
......@@ -187,7 +191,10 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
......@@ -201,6 +208,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
......@@ -215,7 +223,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0xf);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
......@@ -266,7 +277,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
......@@ -575,13 +589,17 @@ int arm926ejs_arch_state(struct target_s *target)
int arm926ejs_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
target_halt(target);
if((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
long long then=timeval_ms();
int timeout;
......@@ -590,7 +608,10 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
embeddedice_read_reg(dbg_stat);
jtag_execute_queue();
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
} else
{
break;
......@@ -629,10 +650,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
arm926ejs->armv4_5_mmu.mmu_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return ERROR_OK;